• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1131-1132
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• 2008

In this paper, we developed UHF RFID R/W system using AT91SAM7S256(ARM chip), UHF RFID R/W module (WJ7090) and wireless LAN(IEEE 802.11.a/b). And we developed a transmission/receiving packet which is send to UHF R/W module in AT91SAM7S256. In order to show the usefulness of UHF RFID R/W system, we executed a performance test. The developed UHF RFID R/W system shows better performance for reading of RFID tag and data transmission through wireless LAN.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.9-15
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• 2007

In this paper, we present the design of Schottky diodes and voltage multiplier for UHF-band passive RFID applications. The Schottky diodes were fabricated using Titanium (Ti/Al/Ta/Al)-Silicon (n-type) junction in $0.35\;{\mu}m$ CMOS process. The Schottky diode having $4{\times}10{\times}10\;{\mu}m^{2}$ contact area showed a turn-on voltage of about 150 mV for the forward diode current of $20\;{\mu}A$. The breakdown voltage is about -9 V, which provides sufficient peak inverse voltage necessary for the voltage multiplier in the RFID tag chip. The effect of the size of Schottky diode on the turn-on voltage and the input impedance at 900 MHz was investigated using small-signal equivalent model. Also, the effect or qualify factor of the diode on the input voltage to the tag chip is examined, which indicates that high qualify factor Schottky diode is desirable to minimize loss. The fabricated voltage multiplier resulted in a output voltage of more than 1.3 V for the input RF signal of 200mV, which is suitable for long-range RFID applications.

• Journal of the Korean Data and Information Science Society
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• v.20 no.1
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• pp.125-137
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• 2009

Smart card has a small sized micro computer chip. This chip contains processor, RAM, ROM, clock, bus system and crypto-co-processor. Hence it is more expensive, complicated and secure chip compared with RFID tag. The main application area of smart card is e-banking and secure communications. There are two kinds of smart card platforms; open platform and closed one. Java card is the most popular open platform because of its security, platform independency, fast developing cycle. However, the speed of Java card is slower than other ones, hence there have been hot research topics to improve the performance of Java card. In this paper, we propose an efficient transaction buffer management to improve the performance of Java card. The experimental result shows the advantage of our method.

• ETRI Journal
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• v.35 no.4
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• pp.610-616
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• 2013

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology. The RFID logic circuit generates 16-bit code programmed in read-only memory. All circuits are implemented in a pseudo-CMOS logic style using transparent a-IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300-nm to 800-nm wavelength. The RFID logic chip generates Manchester-encoded 16-bit data with a 3.2-kHz clock frequency and consumes 170 ${\mu}W$ at $V_{DD}=6$ V. It employs 222 transistors and occupies a chip area of 5.85 $mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.302-312
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• 2012

In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.79-85
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• 2004

In this paper, the RF-ID system for ubiquitous tagging applications has been designed, fabricated and analysed. The RF-ID System consists of passive RF-ID Tag and Reader. The passive RF-ID tag consists of rectifier using zero-bias schottky diode which converts RF power into DC power, ID chip, ASK modulator using bipolar transistor and slot loop antenna. We suggest an ASK undulation method using a bipolar transistor to compensate the disadvantage of the conventional PIN diode, which needs large current Also, the slot loop antenna with wider bandwidth than that of the conventional patch antenna is suggested The RF-ID reader consist of patch array antenna, Tx/Rx part and ASK demodulator. We have designed the RF-ID System using EM and circuit simulation tools. According to the measured results, The power level of modulation signal at 1 m from passive RF-ID Tag is -46.76 dBm and frequency of it is 57.2 KHz. The transmitting power of RF-ID reader was 500 mW

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.694-700
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• 2009

In this paper, we propose a RFID tag antenna with low performance degradation due to nearby dielectric materials. The proposed antenna is designed to be appropriate for ink printing fabrication. The antenna is designed to operate in UHF band of $860{\sim}960$ MHz. The antenna uses a T-matching network in the middle of the main body and two parasitic patches in vicinity for complex conjugate matching with a commercial tag chip. In addition, the two parasitic patches induce currents at different dielectric constants of nearby dielectric materials. This can minimize the performance degradation due to nearby dielectric materials. The measured results show the half power matching bandwidth from 844 MHT to 1,268 MHz. It exhibits the reading distance of about 3.5 m in free space when the tag antenna is used with the commercial reader antenna (transmitting power of 20 dBm and the reader antenna gain of 6 dBi). When the tag is attached on dielectric materials of wood and FR4, the resulting reading distances are 2.61 m and 2.51 m, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.1
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• pp.75-82
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• 2009

In this paper, we proposed a U-shaped broadband RFID tag antenna with a parasitic element operating at UHF band. The proposed tag antenna consists of a U-shaped half wavelength dipole antenna and an inverse U-shaped parasitic element inside the U-shaped dipole antenna. In order to have good impedance matching, the commercial tag chip is attached to the lower center of the rectangular shaped feed. On the condition of VSWR<2, the tag antenna had the measured bandwidth of 4.96 % from 882 to 927 MHz and showed the gain deviation of less than 3.16 dB. On the condition of VSWR<5.8, the tag antenna satisfies the worldwide UHF RFID bandwidth and is showed the gain deviation of less than 5.07 dB. The minimum gain deviation characteristic appears near the center of bandwidth which minimizes variation of gain deviation characteristic with respect to the frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.716-722
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• 2017

In this paper, a fully printed NFC tag operating at 13.56 MHz was designed and fabricated using silver nano-paste and carbon ink. The proposed NFC tag has a printed coil with an inductance of $2.74{\mu}H$ on a PI film for application to an NFC tag IC with an internal capacitance of 50 pF. Screen printing technology used in this paper has advantages such as large area printing for mass production, low cost and eco-friendly process compared to conventional PCB manufacturing process. The proposed structure consists of a circular coil implemented as a single layer using silver nano-paste and carbon ink, a jumper pattern for chip mounting between the outer edge and the center of the coil, and an insulation pattern between the coil and the jumper pattern. In order to verify the performance of the proposed NFC tag, we performed the measurements of the printing line width, thickness, line resistance, adhesion and environmental reliability, and confirmed the suitability of the NFC tag based on the full-printed manufacturing method.