• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.476-478
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• 2006

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a $0.25{\mu}m$ CMOS process. In the design a new dynamic D-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates up to 2.5GHz and consumes 3.1mA at 2.5GHz operation.