• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.6
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• pp.23-29
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• 2003

Transonic two-phase flow of Saturated humid air, in which relative humidity is 100%, with various condensation processes around thin airfoils is investigated. The study uses an extended transonic small-disturbance(TSD) model of Rusak and Lee [11, 12] which includes effects of heat addition to the flow due to condensation. Two possible limit types of condensation processes are considered. In the nonequilibrium and homogeneous process, the condensate mass fraction is calculated according to classical nucleation and droplet growth rate models. In the equilibrium process, the condensate mass fraction is calculated by assuming an isentropic process. The flow and condensation equations are solved numerical1y by iterative computations. Results under same upstream conditions describe the flow structure, field of condensate, and pressure distribution on airfoil's surfaces. It is found that flow characteristics, such as position and strength of shock waves and airfoil’s pressure distribution, are different for the two condensation processes. Yet, in each case, heat addition as a result of condensation causes significant changes in flow behavior and affects the aerodynamic performance of airfoils.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.