• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.827-830
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• 2003

This paper proposes an area-efficient FIR filter architecture for sampling rate conversion of hi-fi audio data. Sampling rate conversion(SRC) block converts audio data sampled at 96KHz down to 48KHz sampled data and vice versa. 63-tap FIR filter coefficients have been synthesized that gives 100dB stop band attenuation and 5.2KHz transition bandwidth. Time-shared filter architecture requires only one multiplier and accumulator for 63-tap filter operation. This results in huge hardware saving of up to 10~19 times smaller compared with traditional FIR structure.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권2호
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2014년도 하계학술대회
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• pp.26-27
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• 2014

This paper presents an adaptive interpolation filtering scheme for the High Efficiency Video Coding (HEVC) standard. In regards to interpolation for motion estimation and compensation, the conventional HEVC employs 8-tap and 4-tap filters for luma and chroma samples, respectively. Coefficients in such filters are determined by discrete cosine transform (DCT). In the proposed scheme, boundary strength values are stored after the execution of the deblocking filter. For each block, the sum of boundary strength values is calculated to indicate whether its region is complex or simple. Consequently, based on the region classification, 12-tap and 8-tap interpolation filters are used for complex and simple regions, respectively. This process is applied to luma sample interpolation only. Simulation results show 1.8% average BD-rate reduction compared to the conventional method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.225-227
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• 2009

International standard specification, H.264/SVC improved from H.264/AVC, is set up so as to promote free use of huge multimedia data in various channel environments.;H.264/AVC is a international standard speicification for video compression, adopted and commercialized as standard for DMB broadcasting by JVT of ISO/IEC MPEG and ITU-T VCEG. SVC standard uses 'intra/inter prediction' in AVC as well as 'inter-layer intra prediction', 'inter-layer motion prediction' and 'inter-layer residual prediction' to improve efficiency of encoding. Among prediction technologies, 'inter-layer intra prediction' is to use co-located block of up sampled sublevels as a prediction signal. At this time, application of interpolation is one of the most important factors to determine encoding efficiency. SVC's currently using poly-phase FIR filter of 4-tap and 2-tap respectively to luma components. This paper is written for the purpose of analyzing encoding performance according to the interpolation. For this purpose, we applied poly-phase FIR filter of '2-tap', '4-tap' and '6-tap' respectively to luma components and then measured bit-rate, PNSR and running time of interpolation filter. We're expecting that the analysis results of this paper will be utilized for effective application of interpolation filter. SVC standard uses 'intra/inter prediction' in AVC as well as 'inter-layer intra prediction', 'inter-layer motion prediction' and 'inter-layer residual prediction' to improve efficiency of encoding.

• 한국정보통신학회논문지
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• 제12권3호
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• pp.527-533
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• 2008

움직임 보상은 고화질의 실시간 비디오 응용에 있어서 언제나 주된 병목을 초래한다. 따라서 실시간 비디오 응용에서는 움직임 보상을 수행하는 고속의 전용 하드웨어를 필요로 한다. 여러 동영상 부호화 방식에서 영상프레임은 픽셀의 블록으로 분할된다. 일반적으로 움직임 보상은 이전 프레임으로부터 움직임을 추정하여 현재의 블록을 예측하게 된다. 움직임 보상에 사용되는 화소 정밀도가 높을수록 보다. 좋은 성능을 갖지만 연산량은 증가하게 된다. 본 논문에서는 1/4 화소 정밀도를 지원하는 H.264/AVC 부호화기에 적합한 움직임 보상기의 아키텍처를 연구하였다. 설계된 움직임 보상기는 전치 배열과 휘도 6-tap 필터 3개를 사용하여 높은 하드웨어 이용률을 갖게 하였으며 내부 메모리의 크기를 감소시켰다. VHDL을 사용하여 기술하였으며, Xilinx ISE툴을 사용하여 합성하고, Modelsim_6.1i를 사용하여 검증하였다. 설계된 움직임 보상기는 단지 3개의 6-tap 필터만을 사용하면서 매크로블록 당 640 클럭 사이클에 수행하였다. 본 논문에서 제안하는 움직임 보상기는 실시간 비디오 처리를 요구하는 분야에 응용 가능할 것으로 사료된다.

• Journal of information and communication convergence engineering
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• 제11권2호
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• pp.118-123
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• 2013

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.240-240
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• 2000

This paper presents two algorithms based on the concept of the frequency domain adaptive filter(FDAF). First the frequency domain recursive least squares(FRLS) algorithm with the overlap-save filtering technique is introduced. This minimizes the sum of exponentially weighted square errors in the frequency domain. To eliminate discrepancies between the linear convolution and the circular convolution, the overlap-save method is utilized. Second, the sliding method of data blocks is studied Co overcome processing delays and complexity roads of the FRLS algorithm. The size of the extended data block is twice as long as the filter tap length. It is possible to slide the data block variously by the adjustable hopping index. By selecting the hopping index appropriately, we can take a trade-off between the convergence rate and the computational complexity. When the input signal is highly correlated and the length of the target FIR filter is huge, the FRLS algorithm based on the block processing technique has good performances in the convergence rate and the computational complexity.

• Clinical and Experimental Reproductive Medicine
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• 제21권1호
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• pp.63-68
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• 1994

To confirm the overcome of in vitro 2-cell block, ICR mouse I-cell embryos were cultured in CZB media. All embryos in CZB were overcome in vitro 2-cell block and 92% of embryos were developed to the blastocyst at day 4. However, in m-KRB group(control) only 20% of embryos were developed over 2-cell. Any embryos in m-KRB did not develop to the morular stage. Developments and degenerations of ICR mouse I-cell embryos were compared in CZB medium prepared with water of three quality:(l) Milli-Q ultrafiltration water(UF);(2) Milli-Q reverse osmosis water(RO);(3) tap water(TAP). The objective was to evaluate the potential of quality control using ICR mouse 1-cell embryos. The more water was purified, the better embryo developments were supported and the less embryos were degenerated. As a quality control system, the culture of ICR 1-cell mouse embryos in CZB was useful.

• 한국통신학회논문지
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• 제37권6A호
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• pp.464-472
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• 2012

본 논문에서는 연속된 프레임을 갖는 영상의 프레임간 움직임 추정 기법을 응용하여 고해상도 영상을 생성하는 초해상도 기법을 제안한다. 단일 영상을 이용한 초해상도 기법의 경우 영상에서의 고주파 대역을 찾기 위해 확률 및 이산 웨이블릿 변환(discrete wavelet transform: DWT) 기반 등 다양한 방법이 제시되었으나, 연산에 사용할 수 있는 정보가 제한적이라는 문제가 존재한다. 이러한 문제를 해결하기 위해 연속된 프레임을 이용한 초해상도 기법이 다양하게 제안되었다. 연속 프레임 기반 초해상도 기법의 핵심인 입력 저해상도 영상 간 정합(registration)의 정확도는 초해상도 기법의 결과에 큰 영향을 갖는다. 본 논문에서는 영상 간 정합의 정확도를 높이기 위하여 6-tap FIR(finite impulse response) 필터를 부화소(sub-pixel) 단위의 정합에 사용한다. 실험을 통하여 제안하는 기법의 결과영상이 기존의 최단입점(nearest neighborhood), 이중선형(bi-linear), 고등차수(bi-cubic) 보간법 보다는 우수하고 DWT 기반의 초해상도 기법과는 비슷한 성능을 가진다는 것을 확인할 수 있었다.