• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.827-830
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• 2003

This paper proposes an area-efficient FIR filter architecture for sampling rate conversion of hi-fi audio data. Sampling rate conversion(SRC) block converts audio data sampled at 96KHz down to 48KHz sampled data and vice versa. 63-tap FIR filter coefficients have been synthesized that gives 100dB stop band attenuation and 5.2KHz transition bandwidth. Time-shared filter architecture requires only one multiplier and accumulator for 63-tap filter operation. This results in huge hardware saving of up to 10~19 times smaller compared with traditional FIR structure.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.26-27
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• 2014

This paper presents an adaptive interpolation filtering scheme for the High Efficiency Video Coding (HEVC) standard. In regards to interpolation for motion estimation and compensation, the conventional HEVC employs 8-tap and 4-tap filters for luma and chroma samples, respectively. Coefficients in such filters are determined by discrete cosine transform (DCT). In the proposed scheme, boundary strength values are stored after the execution of the deblocking filter. For each block, the sum of boundary strength values is calculated to indicate whether its region is complex or simple. Consequently, based on the region classification, 12-tap and 8-tap interpolation filters are used for complex and simple regions, respectively. This process is applied to luma sample interpolation only. Simulation results show 1.8% average BD-rate reduction compared to the conventional method.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.225-227
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• 2009

International standard specification, H.264/SVC improved from H.264/AVC, is set up so as to promote free use of huge multimedia data in various channel environments.;H.264/AVC is a international standard speicification for video compression, adopted and commercialized as standard for DMB broadcasting by JVT of ISO/IEC MPEG and ITU-T VCEG. SVC standard uses 'intra/inter prediction' in AVC as well as 'inter-layer intra prediction', 'inter-layer motion prediction' and 'inter-layer residual prediction' to improve efficiency of encoding. Among prediction technologies, 'inter-layer intra prediction' is to use co-located block of up sampled sublevels as a prediction signal. At this time, application of interpolation is one of the most important factors to determine encoding efficiency. SVC's currently using poly-phase FIR filter of 4-tap and 2-tap respectively to luma components. This paper is written for the purpose of analyzing encoding performance according to the interpolation. For this purpose, we applied poly-phase FIR filter of '2-tap', '4-tap' and '6-tap' respectively to luma components and then measured bit-rate, PNSR and running time of interpolation filter. We're expecting that the analysis results of this paper will be utilized for effective application of interpolation filter. SVC standard uses 'intra/inter prediction' in AVC as well as 'inter-layer intra prediction', 'inter-layer motion prediction' and 'inter-layer residual prediction' to improve efficiency of encoding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.527-533
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• 2008

Motion compensation always produces the principal bottleneck in the real-time high quality video applications. Therefore, a fast dedicated hardware is needed to perform motion compensation in the real-time video applications. In many video encoding methods, the frames are partitioned into blocks of Pixels. In general, motion compensation predicts present block by estimating the motion from previous frame. In motion compensation, the higher pixel accuracy shows the better performance but the computing complexity is increased. In this paper, we studied an architecture of motion compensator suitable for H.264/AVC encoder that supports quarter-pixel accuracy. The designed motion compensator increases the throughput using transpose array and 3 6-tap Luma filters and efficiently reduces the memory access. The motion compensator is described in VHDL and synthesized in Xilinx ISE and verified using Modelsim_6.1i. Our motion compensator uses 36-tap filters only and performs in 640 clock-cycle per macro block. The motion compensator proposed in this paper is suitable to the areas that require the real-time video processing.

• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.118-123
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• 2013

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.240-240
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• 2000

This paper presents two algorithms based on the concept of the frequency domain adaptive filter(FDAF). First the frequency domain recursive least squares(FRLS) algorithm with the overlap-save filtering technique is introduced. This minimizes the sum of exponentially weighted square errors in the frequency domain. To eliminate discrepancies between the linear convolution and the circular convolution, the overlap-save method is utilized. Second, the sliding method of data blocks is studied Co overcome processing delays and complexity roads of the FRLS algorithm. The size of the extended data block is twice as long as the filter tap length. It is possible to slide the data block variously by the adjustable hopping index. By selecting the hopping index appropriately, we can take a trade-off between the convergence rate and the computational complexity. When the input signal is highly correlated and the length of the target FIR filter is huge, the FRLS algorithm based on the block processing technique has good performances in the convergence rate and the computational complexity.

• Clinical and Experimental Reproductive Medicine
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• v.21 no.1
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• pp.63-68
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• 1994

To confirm the overcome of in vitro 2-cell block, ICR mouse I-cell embryos were cultured in CZB media. All embryos in CZB were overcome in vitro 2-cell block and 92% of embryos were developed to the blastocyst at day 4. However, in m-KRB group(control) only 20% of embryos were developed over 2-cell. Any embryos in m-KRB did not develop to the morular stage. Developments and degenerations of ICR mouse I-cell embryos were compared in CZB medium prepared with water of three quality:(l) Milli-Q ultrafiltration water(UF);(2) Milli-Q reverse osmosis water(RO);(3) tap water(TAP). The objective was to evaluate the potential of quality control using ICR mouse 1-cell embryos. The more water was purified, the better embryo developments were supported and the less embryos were degenerated. As a quality control system, the culture of ICR 1-cell mouse embryos in CZB was useful.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.464-472
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• 2012

In this paper, we propose a new super-resolution algorithm that uses successive frames by applying the block matching motion estimation algorithm. Usually, single frame super-resolution algorithms are based on probability or discrete wavelet transform (DWT) approach to extract high-frequency components of the input image, but only limited information is available for these algorithms. To solve this problem, various multiple-frame based super-resolution algorithms are proposed. The accuracy of registration between frames is a very important factor for the good performance of an algorithm. We therefore propose an algorithm using 6-Tap FIR filter to increase the accuracy of the image registration with sub-pixel unit. Proposed algorithm shows better performance than other conventional interpolation based algorithms such as nearest neighborhood, bi-linear and bi-cubic methods and results in about the same image quality as DWT based super-resolution algorithm.