• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.366-370
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• 2002

A kinematic ball bar measurement system can analyze the various errors of a machine tool easily and rapidly in a procedure and can measure many types of equipment such as chip mounter, PCB router, precision stage, etc. In this paper, the thermally induced errors are loused among various errors of a chip mounter because it affects the accuracy of the machine very much. Linear regression technique is adapted for the thermal error modeling. While the measurement and calibration of a chip mounter is difficult in general, this developed system is not only easy to apply for it but also improves the accuracy by 4 times or more.

• 한국기계가공학회지
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• 제12권6호
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• pp.175-181
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• 2013

The primary element of machining automation is to maximize the utilization of machine tools, which determines the output and lead-time. In particular, 95% of raw materials for wing ribs are cut into chips and 0.6 ton of chips are generated every hour from each machine tool. In order to verify the chip recycling system that controls the chips from the machines in five-axis FMS line, a simulation of the virtual model is constructed using the QUEST simulation program. The optimum speed of the chip conveyor and its operating conditions that directly affect the efficiency of the FMS line are presented including the chip conveyor speed, the maximum capacity of the hopper, and the number of chip compressors.

• 조명전기설비학회논문지
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• 제18권4호
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• pp.160-164
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• 2004

본 논문에서는 근사화된 해석파형을 사용한 DS/CDMA 시스템에 적용하였다. 제안된 칩 파형은 균일 엔벌로프를 가진 균일칩 파형과 비균일 엔벌로프를 가진 비균일칩 파형의 두 가지로 형태로 분류한다. 근사화된 해석칩 파형의 단순성은 칩파형, 엔벨로프, 위상, 상관관계와 대역폭 성질 등을 비교하고 증명하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 춘계학술대회 논문집
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• pp.477-480
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• 1995

Dccisions of optimal filling conditions for the chip encapsulation have been done primarily by an ad hoc use of expertise accumulated over the years because the chip encapsulation process is quite complicated. The current CAE systems do not provide mold designers with necessary knowledge of the chip encapsulation for the successful design of optimal filling except flow simulation capability. There have been no attempts to solve the optimal filling problem in the process of the chip encapsulation. In this paper, we have constructed an design system for optimal filling to avoid short shot in the chip encapsulation process which combines an optimization methodology with CAE software.

• International Journal of Precision Engineering and Manufacturing
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• 제6권3호
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• pp.24-28
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• 2005

Stress state of chip formation zone is one of the main problems in metal cutting mechanics. In two-dimensional case this process is usually considered as consistent shears of work material along one of several shear surfaces, separating chip from workpiece. These shear planes are assumed to be trajectories of maximum shear stress forming corresponding slip-line field. This paper suggests a new approach to the constriction of slip-line field, which implies uniform compression in chip formation zone. Based on the given model it has been found that imaginary shear line in orthogonal cutting is close to the trajectory of maximum normal stress and the problem about its determination has been considered as well. It has been shown that there is a second central slip-line field inside chip, which corresponds well to experimental data about stress distribution on tool rake face and tool-chip contact length. The suggested model would be useful in understanding mechanistic problems in machining.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.408-411
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• 1999

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1102-1104
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• 2000

Recently effective system-on-a-chip design methodology is developed, and ASIC chip design is much studied for motor control. This paper investigates the design and implementation of ASIC chip for sensorless speed control of induction motor using VHDL which is a standarded hardware description language. The sensorless control strategy is to design an adaptive state observer for flux estimation and to estimate the rotor speed from the estimated rotor flux and stator current. The presented system is implemented using a simple electronic circuit based on FPGA.

• 조명전기설비학회논문지
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• 제19권1호
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• pp.64-69
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• 2005

본 논문에서는 DS/CDMA 통신 시스템의 비선형 성능 분석하였다. 또한, 선형일 때 기존의 칩 파형 중 성능이 가장 우수한 Raised cosine 칩 파형과 비교하면 $BER=10^{-4}$을 기준으로 균일 칩 파형은 거의 유사한 성능을 갖지만, 비균일 칩 파형은 0.5[dB] 전력 이득을 찾아서 제안한 칩 파형 중 MAI를 최소화하는 최적의 칩 파형임을 알 수 있었다. 그러나 비선형일 때는 비균일 칩 파형의 높은 PAPR로 인하여 균일 칩 파형에 비해 좋지 않은 성능을 보였다. 즉 비균일 칩 파형이 사용된 비선형 CDMA 시스템에서 약 15[dB]정도의 IBO를 해야 선형 증폭기를 통과한 시스템의 성능과 같아지게 됨을 알 수 있었다.

• 한국전자파학회논문지
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• 제20권12호
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• pp.1264-1271
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• 2009

본 논문에서는 이동 무선 통신 기기에 적합하고 다중 대역에서 동작하도록 설계된 칩 슬롯 안테나를 제안하였다. 제안된 안테나는 시스템 회로 기판(30 mm$\times$60 mm$\times$0.8 mm) 위에 칩 안테나(10 mm$\times$20 mm$\times$1.27 mm)를 접속시킨 구조이며, 안테나의 F자 형태의 패턴의 끝단은 비아를 통해 시스템 회로 기판과 연결되어졌다. 따라서 칩 안테나는 시스템 회로 기판의 마이크로스트립 선로로부터 접지면 슬롯 사이의 전이(transition)를 통하여 효과적으로 에너지를 방사한다. 제작된 안테나의 측정 결과 3:1 VSWR 임피던스 대역폭($\leq$-6 dB)은 1.98 GHz(1.61~3.59 GHz)와 0.8 GHz(5.2~6 GHz)로 나타났다. 제안된 안테나는 DCS, PCS, UMTS, WLAN의 주파수 대역을 만족함으로 무선 통신 기기에 적용 가능할 것으로 사료된다.