• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.366-370
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• 2002

A kinematic ball bar measurement system can analyze the various errors of a machine tool easily and rapidly in a procedure and can measure many types of equipment such as chip mounter, PCB router, precision stage, etc. In this paper, the thermally induced errors are loused among various errors of a chip mounter because it affects the accuracy of the machine very much. Linear regression technique is adapted for the thermal error modeling. While the measurement and calibration of a chip mounter is difficult in general, this developed system is not only easy to apply for it but also improves the accuracy by 4 times or more.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.6
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• pp.175-181
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• 2013

The primary element of machining automation is to maximize the utilization of machine tools, which determines the output and lead-time. In particular, 95% of raw materials for wing ribs are cut into chips and 0.6 ton of chips are generated every hour from each machine tool. In order to verify the chip recycling system that controls the chips from the machines in five-axis FMS line, a simulation of the virtual model is constructed using the QUEST simulation program. The optimum speed of the chip conveyor and its operating conditions that directly affect the efficiency of the FMS line are presented including the chip conveyor speed, the maximum capacity of the hopper, and the number of chip compressors.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.4
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• pp.160-164
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• 2004

In DS/CDMA(direct sequence code division multiple access) system using the approximated analytic chip waveforms are applied. Proposed chip waveforms are classified into 2 types: uniform chip waveforms with uniform envelope and non-uniform chip waveforms with non-uniform envelope. It has confirmed that the similarity of the approximated analytical chip waveforms is compared using chip waveforms, envelope, phase, correlation, and bandwidth properties.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.04b
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• pp.477-480
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• 1995

Dccisions of optimal filling conditions for the chip encapsulation have been done primarily by an ad hoc use of expertise accumulated over the years because the chip encapsulation process is quite complicated. The current CAE systems do not provide mold designers with necessary knowledge of the chip encapsulation for the successful design of optimal filling except flow simulation capability. There have been no attempts to solve the optimal filling problem in the process of the chip encapsulation. In this paper, we have constructed an design system for optimal filling to avoid short shot in the chip encapsulation process which combines an optimization methodology with CAE software.

• International Journal of Precision Engineering and Manufacturing
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• v.6 no.3
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• pp.24-28
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• 2005

Stress state of chip formation zone is one of the main problems in metal cutting mechanics. In two-dimensional case this process is usually considered as consistent shears of work material along one of several shear surfaces, separating chip from workpiece. These shear planes are assumed to be trajectories of maximum shear stress forming corresponding slip-line field. This paper suggests a new approach to the constriction of slip-line field, which implies uniform compression in chip formation zone. Based on the given model it has been found that imaginary shear line in orthogonal cutting is close to the trajectory of maximum normal stress and the problem about its determination has been considered as well. It has been shown that there is a second central slip-line field inside chip, which corresponds well to experimental data about stress distribution on tool rake face and tool-chip contact length. The suggested model would be useful in understanding mechanistic problems in machining.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.408-411
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• 1999

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1102-1104
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• 2000

Recently effective system-on-a-chip design methodology is developed, and ASIC chip design is much studied for motor control. This paper investigates the design and implementation of ASIC chip for sensorless speed control of induction motor using VHDL which is a standarded hardware description language. The sensorless control strategy is to design an adaptive state observer for flux estimation and to estimate the rotor speed from the estimated rotor flux and stator current. The presented system is implemented using a simple electronic circuit based on FPGA.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.1
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• pp.64-69
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• 2005

In this paper, we analyzed the nonlinear performance on the DS/CDMA Communication System. At the $BER=10^{-4}$, uniform chip waveforms have similar performance in the linear channel. However, non-uniform chip waveforms have about more 0.5[dB] power gain than the conventional raised-cosine chip waveforms. In the nonlinear HPA, non-uniform chip waveforms have worse BER performance than the uniform chip waveforms because of the high PAPR. In other words, non-uniform chip waveforms show similar performance as uniform chip waveforms if IBO (input back on) of 15[dB] is given.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1264-1271
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• 2009

In this paper, the chip slot antenna which is used for mobile devices and designed for multi-band is proposed. The proposed antenna is comprised of a chip antenna(10 mm$\times$20 mm$\times$1.27 mm) and a system circuit board(30 mm$\times$60 mm$\times$0.8 mm). The chip slot antenna is mounted on the system circuit board and the end of F-type strip line which is patterned on the chip antenna is connected by a via with a ground plane of the system circuit board. So, a chip antenna radiates effectively the energy by transition between a microstrip line of the system circuit board and a open slot structure of the chip antenna. In the results of proposed antenna, impedance bandwidth of 3:1 VSWR(-6 dB return loss) is 1.98 GHz(1.61~3.59 GHz) and 0.8 GHz(5.2~6 GHz). So, it can cover multi-band of DCS, PCS, UMTS, WLAN. The proposed antenna can be applied to mobile devices.