• 한국시뮬레이션학회논문지
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• 제8권4호
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• pp.137-154
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• 1999

In this paper, we propose a software design method that will track the effects of modifications in a component to the rest of the components in the design phase. The prediction of the effects due to the design modifications before coding can be a valuable aid for the complex and large software development. Within the method, the target system is represented by the structured I/O system level specification which is one of the system representation level defined by the system theory. Then it is abstracted to the I/O system level. The DEVS (Discrete Event System Specification) model is constructed based on tile I/O system level specification. Finally, the DEVS model is simulated to generate the behavior of the software by the abstract simulator in DEVS simulation environment. As an application, the graphic user interface system of a metal grating production scheduling system is presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.173-176
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• 2000

Silicon semiconductor technology agree that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduce verification time. This Paper describe the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

• 정보처리학회논문지A
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• 제9A권4호
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• pp.459-466
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• 2002

최근의 내장형 시스템은 유연성을 유지하고 시간 제약사항을 만족하기 위해서 일반적인 프로세서와 FPGA와 같은 재구성 가능한 부품을 결합하는 Hybrid 시스템을 사용하는 추세이다. 이러한 내장형 시스템은 구축하는 설계 시간을 단축하여 짧은 시간 안에 시장에 진입하는 것이 아주 중요하다. 새로이 주목받고 있는 연구분야인 설계공간탐색은 실제 시스템을 제작하지 않고도 시스템 수준에서 어플리케이션의 성능을 분석하여 최소의 비용으로 시스템에서 요구하는 제약사항을 만족하는 구조를 예측하는 것을 가능하게 한다. 본 논문에서는 Hybrid 내장형 시스템의 설계공간탐색을 위한 시간분석 시뮬레이터를 선계하고 구현하였다. 시스템 설계변수를 변화하면서 정량적인 성능 데이타를 이용하여 설계공간 탐색을 가능하게 하는 Y-Chart 방법을 Hybrid 시스템의 경우에 적용하여 시뮬레이터를 확장 구현하였으며, 기존의 소프트웨어 시간 분석 도구 및 하드웨어 시간분석도구를 활용한다. 본 논문에서 제시하는 시간분석 시뮬레이터는 Hybrid 내장형 시스템의 설계 비용과 시간을 현저하게 줄이면서, 최적의 하드웨어 구성을 찾는 설계공간탐색의 핵심 모듈로 활용될 것으로 기대된다.

• 한국정보통신학회논문지
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• 제3권4호
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• pp.755-764
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• 1999

In this study, the system level network simulation is considered with adaptive array antenna in CDMA mobile communication system. A network simulation framework is implemented based on IS-95A/B system to consider dynamic handoff, system level network behavior, and deploying strategy into the overall CDMA mobile communication network under adaptive array algorithm. Its simulation model, such as vector channel model, adaptive beam forming antenna model, handoff model, and power control model, are described in detail with simulation block. In order to maximize SINR of received signal at antenna, maximin algorithm is particularly considered, and it is computed at each simulation snap shot with SINR based power control and handoff algorithm. Graphic user interface in this system level network simulator is also implemented to define the simulation environments and to represent simulation results on real mapping system. This paper also shows some features of simulation framework and simulation results.

• 한국시뮬레이션학회논문지
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• 제8권4호
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• pp.33-51
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• 1999

In this study, the system level network simulation is considered with adaptive array antenna in CDMA mobile communication system. A network simulation framework is implemented based on IS-95A/B system to consider dynamic handoff, system level network behavior, and deploying strategy into the overall CDMA mobile communication network under adaptive array algorithm. Its simulation model, such as vector channel model, adaptive beam forming antenna model, handoff model, and power control model, are described in detail with simulation block. In order to maximize SINR of received signal at antenna, Maximin algorithm is particularly considered, and it is computed at each simulation snap shot with SINR based power control and handoff algorithm. Graphic user interface in this system level network simulator is also implemented to define the simulation environments and to represent simulation results on real mapping system. This paper also shows some features of simulation framework and simulation results.

• 한국군사과학기술학회지
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• 제8권4호
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• pp.58-67
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• 2005

To overcome limitations of test scope, schedule and cost, M&S(Modeling & Simulation) technique has been applied for T&E(Test and Evaluation) of the state-of-art weapon systems. This paper proposes an air defense simulation software framework to reduce both redundancy an[1 programming errors in system simulator. The proposed framework consists of a 'model' and a 'middleware' The 'middleware' is a reliable communication service layer that supports not only HLA(High Level Architecture) which is an international standard in M&S but also TCP/IP, UDP and etc. The main role of 'model' is to schedule and to run the real-time distributed simulation. The proposed framework has been applied to M-SAM(Middle range Surface to Air Missile) system simulator. The proposed framework's scheduling and communication performance results are satisfactory and were measured by hardwired NTP(Network Timer Protocol) time-stamp with GPS(Global Positioning System) timer for better precision.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권7호
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• pp.2548-2567
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• 2015

Recently, there has been a clear trend towards the application of ad hoc networking technology in civil aviation communication systems, giving birth to a new research field, namely, aeronautical ad hoc networks (AANETs). An AANET is a special type of ad hoc wireless network with a significantly larger scale and distinct characteristics of its mobile nodes. Thus, there is an urgent need to develop a simulator to facilitate the research in these networks. In this paper, we present a network simulator, Aero-Sim, for AANETs. Aero-Sim, which is based on the freely distributed NS-2 simulator, enables detailed packet-level simulations of protocols at the MAC, link, network, transport, and application layers by composing simulations with existing modules and protocols in NS-2. Moreover, Aero-Sim supports three-dimensional network deployment. Through several case studies using realistic China domestic air traffic, we show that the proposed simulator can be used to simulate AANETs and can reproduce the real world with high fidelity.

• Journal of Power Electronics
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• 제16권2호
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Journal of Information Display
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• 제5권4호
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• pp.38-44
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• 2004

In this paper, a server and client simulator for the web-based multi-view 3D image communication system is implemented by using the IEEE 1394 digital cameras, Intel Xeon server computer and Microsoft's DirectShow programming library. In the proposed system, two-view image is initially captured by using the IEEE 1394 stereo camera and then, this data is compressed through extraction of its disparity information in the Intel Xeon server computer and transmitted to the client system, in which multi-view images are generated through the intermediate views reconstruction method and finally display on the 3D display monitor. Through some experiments it is found that the proposed system can display 8-view image having a grey level of 8 bits with a frame rate of 15 fps.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1906-1915
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• 1990

A synthesis system generating sequential circuits from a high-level hardware descdription language CHDL, modelling language for Thor functional/behavioral simulator, is developed. In this paper, we describe the semantic analysis process, state minimization and state assignment algorithms. proposed assignment algorithm generates optimal state vectors using constraint matrix and similarity graph. Expremental results for MCNC benchmarks, standard test circuits, show that the system inplementing the proposed algorithms can be a viable tool for designing large finite state machines.