• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.131-137
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• 2016

In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.3-7
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• 2000

In summary, a fundamentally new paradigm called System-on-Package could potentially become a complementary alternative to System-on-Chip, thus providing a balanced set of system-level functions between the semiconductor IC and single component package beyond the year 2007. The concurrent engineering and optimization of IC and package could overcome the fundamental IC issues presented above.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.10
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• pp.2606-2615
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• 1994

Sorting time is one of the most important issues for auto IC test handling systems. In actual system, because of too much path, reducing the computing time for finding a sorting path is the key way to enhancing the system performance. The exhaustive path search technique can not be used for real systems. This paper proposes heuristic sorting algorithm to find the minimal sorting time. The suggested algorithm is basically based on the best-first search technique and multi-level search technique. The results are close to the optimal solutions and computing time is greately reduced also. Therefore the proposed algorthm can be effectively used for real-time sorting process in auto IC test handling systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.73-85
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• 1993

This paper presents a design and implementation of CAD(Computer-Aided Design) system with tools and design environments for IC(Intergrated Circuits)design. The CAD system can be easily installed in various sites with limited resources, since most CAD tools and design environments are available in the public-domain and Unix & X Window-based PC-386 and Workstation is used for the hardware platform. In order to improve the flexibility of the CAD system, objects are defined in the context of tools and environments` and object tables are programmed to describe the integration of CAD tools and design environments. During the execution, tool-objects deal with intertool communication and round-robin mechanism to incrementally control the execution of CAD tools. The IC design of LPC(Linear Predictive Coding) Speech Synthesizer is carried out to find out improvements and bugs of the CAD system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04a
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• pp.25-28
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• 2002

Contact type Ic measurement system is needed to measure Ic continuously for long Bi-2223 tapes. Voltage and current terminals were designed several shapes for 4-probe method Ic measurement. Voltage terminals were made with brass and current terminals were made with Cu. We used 2 kinds of Bi-2223 tapes with different strength. When we measured Ic of Bi-2223 tape with Ag-Mg sheath, The proper weight was 0.3 kg and sharp pin type was better. according to voltage terminal shape and load. In case of Bi-2223 tape with Ag-Mn sheath, the proper terminal weight was 4 kg and sharp pin type was bad. It was possible to make continuous contact type Ic measurement system because We could get proper data - terminal shapes and loads - through these experiments.

• ETRI Journal
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• v.37 no.6
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• pp.1165-1175
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• 2015

This paper presents an advanced sensorless permanent magnet (PM) brushless motor controller integrated circuit (IC) employing an automatic lead-angle compensator. The proposed IC is composed of not only a sensorless sine-wave motor controller but also an isolated gate-driver and current self-sensing circuit. The fabricated IC operates in sensorless mode using a position estimator based on a sliding mode observer and an open-loop start-up. For high efficiency PM brushless motor driving, an automatic lead-angle control algorithm is employed, which improves the efficiency of a PM brushless motor system by tracking the minimum copper loss under various load and speed conditions. The fabricated IC is evaluated experimentally using a commercial 200 W PM brushless motor and power switches. The proposed IC is successfully operated without any additional sensors, and the proposed algorithm maintains the minimum current and maximum system efficiency under $0N{\cdot}m$ to $0.8N{\cdot}m$ load conditions. The proposed IC is a feasible sensorless speed controller for various applications with a wide range of load and speed conditions.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.195-200
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• 2006

The conventional discrete circuit for ABS/TCS system was examined and the problems of the system were analyzed by computer simulation. In order to improve the performance of ABS/TCS system, interface IC which has error compensation, comparator and under voltage lock-out circuit was designed and their electrical characteristics were investigated. The voltage regulator was included to compensate the temperature variation in the temperature range from $-20^{\circ}C$ to $120^{\circ}C$ for automobile environment. ABS and brake signal were separated using the duty factor of same frequency or different frequencies. UVLO(Under Voltage Lock-Out) circuit and constant current circuit were applied for the elimination of noise, and protection circuit was applied to cut the excess current off. Layout for IC fabrication was designed to enhance the electrical performance of ABS/TCS system. Layout was consisted of 11 masks, arrayed effectively 8 pads to reduce the current loss. We can see that the result of layout simulation was better than the result of bread board.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.276-281
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• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2831-2834
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• 2003

본 논문에서는 PWM 방식을 이용한 THERMO-CON 제어 회로를 제안하였다. 제안한 회로는 정전압을 형성하기 위한 레귤레이터, 신호를 처리하기 위한 op-amp, 삼각파를 만들기 위한 OSC, 그리고 부하의 상태를 감지하기 위한 AMC 와 ISC 로 구성된다. 테스트 결과 서지 전압인가 시 PWM 방식으로 동작하여 회로의 P/sub D/(Power Dissipation)을 줄여 소자의 파괴를 막고 중부하 시(여러 개의 릴레이 구동 시) PWM 동작을 하여 소자의 파괴를 막는다는 것을 확인하였으며, 출력 쇼트 시 쇼트보호회로에 의해 출력 트랜지스터의 파괴를 막는다는 것을 확인하였다.