• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.5-12
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• 1997

In this paper, the 3 operator FM synthesis method has been devised on the basis of the analysis of Gayageum sounds. The parameters for the proposed synthesis algorithm has been implemented by C language. It is subjectively and objectively confirmed that the sounds synthesized by C language are very similar to the original sounds. The synthesis algorithm is also implemented by DSP, and the sounds from this experiment are close to the original ones.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.149-157
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• 1994

This paper Presents an algorithm for synthesis of sequential statements described at RT level VHDL. The proposed algorithm transforms sequential statements in VHDL into data-flow description consisting of concurrent statements by local and global dependency analysis and output dependency elimination. Transformation into concurrent statements makes it possible to reduce the cost of the synthesized hardwares, thus to get optimal synthesis results that will befit the designer 's intention. This algorithm has been implemented on VSYN and experimental results show that more compact gate-level hardwares are generated compared with Power View system from ViewLogic and Design Analyzer from Synopsys.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2002.05a
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• pp.273-277
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• 2002

This paper describes an optimal synthesis method of binary neural network(BNN) for an approximation problem of a circular region and synthetic image having four class using a newly proposed learning algorithm. Our object is to minimize the number of connections and neurons in hidden layer by using a Newly Expanded and Truncated Learning Algorithm(NETLA) based on the multilayer BNN. The synthesis method in the NETLA is based on the extension principle of Expanded and Truncated Learning (ETL) learning algorithm using the multilayer perceptron and is based on Expanded Sum of Product (ESP) as one of the boolean expression techniques. The number of the required neurons in hidden layer can be reduced and fasted for learning pattern recognition.. The superiority of this NETLA to other algorithms was proved by simulation.

• Journal of Microbiology and Biotechnology
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• v.11 no.3
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• pp.384-388
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• 2001

The metabolic pathway synthesis algorithm was applied to estimate the maximum ethanol yield from xylose in a model recombinant Saccharomyces cerevisiae strain containing the genes involved in xylose metabolism. The stoichiometrically independent pathways were identified by constructing a biochemical reaction network for conversion of xylose to ethanol in the recombinant S. cerevisiae. Two independent pathways were obtained in xylose-assimilating recombinant S. cerevisiae as opposed to six independent pathways for conversion of glucose to ethanol. The maximum ethanol yield from xylose was estimated to be 0.46 g/g, which was lower than the known value of 0.51 g/g for glucose-fermenting and wild-type xylose-fermenting yeasts.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.476-478
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• 2015

This paper deals with synthesis of 4 bar linkage by using optimum design. To design 4 bar linkage, overlay method is proposed and for optimization, genetic algorithm is applied with objective function. The accuracy of this method will be determined by errors between real value and test value. We will use Chebychev spacing to get 3 precision positions of input angles. The output angles will be determined by the function that the designer wants input and output relations to be. It will be applied to example to show the accuracy of this method. The advantages of using this method are that it is fast to get optimal solution and it is simple to use.

• Speech Sciences
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• v.8 no.4
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• pp.35-43
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• 2001

New speech synthesis algorithms capable of flexible prosody (especially F0) modification are desired for a high quality TTS system. TD-PSOLA is the most popular synthesis algorithm. The algorithm shows very high quality when F0 modification is limited. However, the quality degradation due to pitch epoch detection error becomes severe as the F0 modification factor becomes large. On the other hand, the vocoder framework is very flexible in F0 manipulation. The synthesized speech quality from the vocoder is far from natural human speech and suffers from buzziness. To remedy the buzzy quality from the vocoder and make more natural synthetic speech, we propose a mixed phase vocoder.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.4
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• pp.492-499
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• 2016

Null pattern synthesis method using the Quantum-inspired Evolutionary Algorithm(QEA) is described in this study. A $12{\times}12$ planar array antenna is considered and each element of the array antenna is controlled by 6-bit phase shifter. The maximum number of iteration of 500 is used in simulation and the rotation angle for updating Q-bit individuals is determined to make the individual converge to the best solution and is summarized in a look-up table. In this study we showed that QEA can satisfactorily synthesize the null pattern using smaller number of individuals compared with the conventional Genetic Algorithm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.46-58
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• 1998

In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.454-468
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• 1997

This paper presents a bitwidth optimization algorithm for efficient hardware sharing in digital signal processing system. The proposed algorithm determines the fixed-point representation for each signal through bitwidth optimization to generate the hardware requiring less area. To reduce the operator area, the algorithm partitions the abstract operations in the design description into several groups, such that the operations in the same group can share an operator. The partitioning result are fed to a high-level synthesis system to generate the pipelined fixed-point datapaths. The proposed algorithm has been implemented in SODAS-DSP an automatic synthesis system for fixed-point DSP hardware. Accepting the models of DSP algorithms in schematics, the system automatically generates the fixed-point datapath and controller satisfying the design constraints in area, speed, and SNR(Signal-to-Noise Ratio). Experimental results show that the efficiency of the proposed algorithm by generates the area-efficient DSP hardwares satisfying performance constraints.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.105-108
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• 2002

Although asynchronous designs have become a promising way to develop complex modern digital systems, there is a few complete design framework for VLSI designers who wish to use automatic CAD tools. Especially, high-level synthesis is not widely concerned until now. In this paper we Proposed a method for high-level synthesis of asynchronous systems as a part of an asynchronous design framework. Our method performs scheduling, allocation, and binding, which are three subtasks of high-level synthesis, in simultaneous using a transformational approach. To deal with complexity of high-level synthesis we use neighborhood search algorithm such as Tabu search.