• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.11
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• pp.404-416
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• 1983

This paper is concerned with the design automation of the sequential machines. The operations of sequential machine can be diveded into two types such as synchronous and asynchronous sequential machine and their realization is treated in separate mode. But, in order to integrate logic circuits in high volume, mixed mode sequential machine uses common circuitry that consists of gates and flip-flops. Proposed sequential machine can be designed by several method, which are hard-wired implementation, firmware realization by PLA and ROM. And then onr example shows the differnces among three design mothods. Finally, computer algorithm(called MINIPLA) is discussed for various application of mixed-mode sequential machine.

• Proceedings of the KAIS Fall Conference
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• 2001.05a
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• pp.169-172
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• 2001

본 논문은 ATMEL Bluetooth Development Kit (DK)를 이용하여 음성과 데이터를 전송하는 시스템을 구현하는 것으로, Bluetooth 디바이스간 연결을 위한 과정을 분석하였다. 또한, Synchronous Connection-Oriented (SCO) 링크와 Asynchronous Connectionless (ACL) 링크를 형성하여 음성과 데이터를 송수신하는 어플리케이션을 구현하였다. 향후 가정, 사무실, 공장 등에서 근거리 무선 통신 기술로 자리잡아갈 Bluetooth 기술을 적용한 어플리케이션 개발은 필수적이다. 본 논문에서는 Bluetooth 호스트 컨트롤러 인터페이스(HCI)를 이용한 어플리케이션 개발 과정을 제시하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.1
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• pp.53-59
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• 2017

This Paper Proposes a New High-speed Design Methodology for Delay Insensitive Asynchronous Circuits Combining with a Pseudo-NMOS Structure used for High Performance in Synchronous Circuits. Null Convention Logic(NCL) of Conventional Delay-Insensitive Asynchronous Design Methodologies has many Advantages of High Reliability, Low Power Consumption, and Easy Design Reuses not Dependant on Semiconductor Technology. However. the Conventional NCL Gates has a Complicated Stack Structure, so it Suffers from Increased Circuit Delay. Therefore, a New NCL Gates and its Pipeline Structure for High Performance, and the Proposed Methodology has been Designed and Evaluated by a $4{\times}4$ Multiplier Designed using SK-Hynix 0.18 um CMOS Technology. The Experimental Results are Compared with a Conventional NCL in Terms of Power and Delay and shows that the Propagation Delay of the Proposed Multiplier is Reduced by 85% Compared with the Conventional NCL Multiplier.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.19-25
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• 2004

In this paper, we propose optimal and suboptimal serial code acquisition schemes for chip-asynchronous direct-sequence spread-spectrum systems. The conventional serial code acquisition scheme is to compare each value of correlator outputs with a threshold individually. However, such a scheme is optimum only under the chip-synchronous assumption which is actually very difficult to be held prior to acquisition at the receiver because the signal-to-noise ratios before despreading are very low. In this paper, an optimal serial code acquisition scheme is derived based on the maximum-likelihood criterion under the more realistic and general chip-asynchronous environments. A suboptimal scheme, which is simpler but yields comparable performance to the optimal one, is also derived based on the criterion of local detection power Numerical results show that, under the chip-asynchronous environments, both the optimal and suboptimal serial code acquisition schemes outperform the conventional serial code acquisition scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2072-2079
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• 1998

In this paper, we propose a new decorrelating detector called pseudo-inverse-filtering type decorrelating detector for asynchronous CDMA channels. We first show that the matched filtering and decorrelating operations of the existing decorrelating detectors can be replaced with the pseudo-inverse filtering operations in synchronous channels, and using this fact we show that the decorrelating detector has the largest SNR among the linear detectors that can eliminate MAI. Then we introduce asynchronous pseudo-inverse filtering type decorrelating detector by extending this result for asynchronous channels, and discuss implementation methods of the proposed decorrelating detectors. Since the proposed scheme employs a decentralized structure for updating coefficients, it has the flexibility to add/remove users. Finally we analyze the performance of the proposed decorrelating detector in terms of the bit error rate, and examine its performance improvements over the conventional detectors through computer simulations.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.10
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• pp.3361-3377
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• 2014

Synchronous computing models provided by real-time synchrony protocols, such as TTA [1] and PALS [2], greatly simplify the design, implementation, and verification of real-time distributed systems. However, their application to real systems has been limited since their assumptions on underlying systems are hard to satisfy. In particular, most previous real-time synchrony protocols hypothesize the existence of underlying fault tolerant real-time networks. This, however, might not be true in most soft real-time applications. In this paper, we propose a practical approach to a synchrony protocol, called Quality-Aware PALS (qPALS), which provides the benefits of a synchronous computing model in environments where no fault-tolerant real-time network is available. qPALS supports two flexible global synchronization protocols: one tailored for the performance and the other for the correctness of synchronization. Hence, applications can make a negotiation flexibly between performance and correctness. In qPALS, the Quality-of-Service (QoS) on synchronization and consistency is specified in a probabilistic manner, and the specified QoS is supported under dynamic and unpredictable network environments via a control-theoretic approach. Our simulation results show that qPALS supports highly reliable synchronization for critical events while still supporting the efficiency and performance even when the underlying network is not stable.

• The Journal of the Acoustical Society of Korea
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• v.19 no.2E
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• pp.8-13
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• 2000

In this paper, we present an adaptive formant tracking algorithm for speech using closed phase WRLS-VFF-VT method. The pitch synchronous closed phase methods is known to give more accurate estimates of the vocal tract parameters than the pitch asynchronous method. However the use of a pitch-synchronous closed phase analysis method has been limited due to difficulties associated with the task of accurately isolating the closed phase region in successive periods of speech. Therefore we have implemented the pitch synchronous closed phase WRLS-VFF-VT algorithm for speech analysis, especially for formant tracking. The proposed algorithm with the variable threshold(VT) can provide a superior performance in the boundary of phone and voiced/unvoiced sound. The proposed method is experimentally compared with the other method such as two channel CPC method by using synthetic waveform and real speech data. From the experimental results, we found that the block data processing techniques, such as the two-channel CPC, gave reasonable estimates of the formant/antiformant. However, the data windows used by these methods included the effects of the periodic excitation pulses, which affected the accuracy of the estimated formants. On the other hand the proposed WRLS-VFF-VT method, which eliminated the influence of the pulse excitation by using an input estimation as part of the algorithm, gave very accurate formant/bandwidth estimates and good spectral matching.

• Proceedings of the Korean Society of Computational and Applied Mathematics Conference
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• 2003.09a
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• pp.11-11
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• 2003

오늘날 단일 슈퍼컴퓨터로는 처리가 불가능한 거대한 문제들의 해법이 시도되고 있는데, 이들은 지리적으로 분산된 슈퍼컴퓨터, 데이터베이스, 과학장비 및 디스플레이 장치 등을 초고속 통신망으로 연결한 GRID 환경에서 효과적으로 실행시킬 수 있다. GRID는 1990년대 중반 과학 및 공학용 분산 컴퓨팅의 연구 과정에서 등장한 것으로, 점차 응용분야가 넓어지고 있다. 그러나 GRID 같은 분산 환경은 기존의 단일 병렬 시스템과는 많은 점에서 다르며 이전의 기술들을 그대로 적용하기에는 무리가 있다. 기존 병렬 시스템에서는 주로 동기 알고리즘(synchronous algorithm)이 사용되는데, 직렬 연산과 같은 결과를 얻기 위해 동기화(synchronization)가 필요하며, 부하 균형이 필수적이다. 그러나 부하 균형은 이질 클러스터(heterogeneous cluster)처럼 프로세서들의 성능이 서로 다르거나, 지리적으로 분산된 계산자원을 사용하는 GRID 환경에서는 이기종의 문제뿐 아니라 네트워크를 통한 메시지의 전송 지연 등으로 유휴시간이 길어질 수밖에 없다. 이처럼 동기화의 필요성에 의한 연산의 지연을 해결하는 하나의 방안으로 비동기 반복법(asynchronous iteration)이 나왔으며, 지금도 활발히 연구되고 있다. 이는 알고리즘의 동기점을 가능한 한 제거함으로써 빠른 프로세서의 유휴 시간을 줄이는 것이 목적이다. 즉 비동기 알고리즘에서는, 각 프로세서는 다른 프로세서로부터 갱신된 데이터가 올 때까지 기다리지 않고 계속 다음 작업을 수행해 나간다. 따라서 동시에 갱신된 데이터를 교환한 후 다음 단계로 진행하는 동기 알고리즘에 비해, 미처 갱신되지 않은 데이터를 사용하는 경우가 많으므로 전체적으로는 연산량 대비의 수렴 속도는 느릴 수 있다 그러나 각 프로세서는 거의 유휴 시간이 없이 연산을 수행하므로 wall clock time은 동기 알고리즘보다 적게 걸리며, 때로는 50%까지 빠른 결과도 보고되고 있다 그러나 현재까지의 연구는 모두 어떤 수렴조건을 만족하는 선형 시스템의 해법에 국한되어 있으며 비교적 구현하기 쉬운 공유 메모리 시스템에서의 연구만 보고되어 있다. 본 연구에서는 행렬의 주요 고유쌍을 구하는 데 있어 비동기 반복법의 적용 가능성을 타진하기 위해 우선 이론적으로 단순한 멱승법을 사용하여 실험하였고 그 결과 순수한 비동기 반복법은 수렴하기 어렵다는 결론을 얻었다 그리하여 동기 알고리즘에 비동기적 요소를 추가한 혼합 병렬 알고리즘을 제안하고, MPI(Message Passing Interface)를 사용하여 수원대학교의 Hydra cluster에서 구현하였다. 그 결과 특정 노드의 성능이 다른 것에 비해 현저하게 떨어질 때 전체적인 알고리즘의 수렴 속도가 떨어지는 것을 상당히 완화할 수 있음이 밝혀졌다.

• Journal of Advanced Navigation Technology
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• v.6 no.1
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• pp.77-83
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• 2002

The emergence of Bluetooth as a radio interface scheme has allowed electronic devices to be instantly interconnected as ad-hoc networks. These short range ad-hoc wireless networks are called piconets, operated in the unlicensed 2.45 GHz ISM(Industrial, Scientific, Medical) band where up to eight devices may be used to configure single or overlapping piconets. In this paper, we have simulated the PER(Packet Error Rate), the ratio of received packet and payload BER(Bit Error Rate) of piconet with packet types of Bluetooth ACL/SCO(Asynchronous Connection Less/Synchronous Connection Oriented) link over wireless ad-hoc environment. The Rayleigh fading effects are considered as channel model, and the simulation results are based on the baseband model of Bluetooth specification. From the simulation results, the PER and the throughput of Bluetooth piconet are sensibly affected by the packet type of ACL/SCO link.

• Asian Pacific Journal of Cancer Prevention
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• v.15 no.14
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• pp.5535-5538
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• 2014

Background: To determine the amount of co-expression of IDO and EGFR in breast cancer patients. Materials and Methods:In order to obtain the distribution of co-expression of IDO and EGFR in breast cancer, we tested 110 breast cancer paraffin tissue blocks with immunohistochemical methods. Then we investigated the relationship between the diagnostic and pathologic characteristics (tumor size, lymph node status, histologic grade, the gene expression of ER, PR, HER2, p53, Ki67 and PCNA) with the situation of co-expression of IDO and EGFR by reviewing the medical records of 32 breast cancer patients. Results: Among 110 breast cancers, 32 cases demonstrated IDO and EGFR co-expression (29.1%), IDO and EGFR synchronous co-expression being found in 19.1% and asynchronous in 10.0%. Conclusions: IDO and EGFR were co-expressed in breast cancer, including synchronous and asynchronous co-expression. The results suggest that considering IDO and EGFR as two indicators for breast cancer treatment or prognosis analysis provides a potential option of individual treatment for the portion of breast cancer patients with co-expression of IDO and EGFR.