• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.38-46
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• 1992

In this thesis, a high speed code synchronization circuit is implemented, which is applicable to frequency hopping FSK tranceiver within 68-88 MIBz band- width. synchronization Process consists of two steps, initial synchronization and tracking. A modified matched filter method using two channel passive correlators matched with short hopping frequencies, synchronization prcfix. is proposed for initial synchronization. To increase probability of initial synchronization, prefix are transmitted repeatedly. The outputs of correlators are sent to synchronization decision circuit, and code start time Is extracted by synchronizatlon decision circuit-Modified matched fitter method makes it possible to reduce complexity in hardware and obtain code acquisition rapidly.Clock recovery circuit regenerates PN code clock for tracking.

• Journal of Communications and Networks
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• v.14 no.5
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• pp.501-509
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• 2012

This paper proposes a joint timing synchronization, channel estimation, and data detection for the impulse radio ultra-wideband systems. The proposed timing synchronizer consists of coarse and fine timing estimation. The synchronizer discovers synchronization points in two stages and performs adaptive threshold based on the maximum pulse averaging and maximum (MAX-PA) method for more precise synchronization. Then, iterative channel estimation is performed based on the discovered synchronization points, and data are detected using the selective rake (S-RAKE) detector employing maximal ratio combining. The proposed synchronizer produces two signals-the start signal for channel estimation and the start signal for start frame delimiter (SFD) detection that detects the packet synchronization signal. With the proposed synchronization, channel estimation, and SFD detection, an S-RAKE receiver with binary pulse position modulation binary phase-shift keying modulation was constructed. In addition, an IEEE 802.15.4a channel model was used for performance comparison. The comparison results show that the constructed receiver yields high performance close to perfect synchronization.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.429-436
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• 2014

This paper proposes three methods of the time synchronization for Pseudolite and GPS and analyzes pseudolite time synchronization error factors for software based performance evaluation on proposed time synchronization methods. Proposed three time synchronization methods are pseudolite time synchronization station construction method, method by using UTC(KRIS) clock source and GPS timing receiver based time synchronization method. Also, we analyze pseudolite time synchronization error factors such as errors of pseudolite clock and reference clock, time delay as clock transmission line, measurement error of time interval counter and error as clock synchronization algorithm to design simulation platform for performance evaluation of pseudolite time synchronization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.4
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• pp.567-573
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• 2002

In this paper, we propose a new symbol time synchronization scheme suitable for the OFDM system with an interpolator. The proposed scheme performs the following three steps. In the first step, the coarse symbol time synchronization is achieved by continuously measuring the average power of the received envelope signal. Based on this average power, the detection possibility for the symbol time synchronization is determined. It the signal is sufficient for synchronization, we next perform a relatively accurate symbol time synchronization by measuring the correlation between a short training signal and the received envelope signal. Finally, an additional frequency synchronization is performed with a long training signal to correct symbol synchronization errors caused by the phase rotation. From the simulation results, one can see that the proposed synchronization scheme provides a good synchronization performance over frequency selective channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.65-76
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• 2004

In this paper, a novel preamble structure, including a synchronization preamble and a cell search preamble, is proposed for OFDM-based cellular systems. An efficient algorithm for downlink synchronization and cell searching using the preamble is also proposed. The synchronization process includes the initial symbol timing estimation using continuously, or at least, periodically transmitted downlink signal, frame synchronization, the fine symbol timing estimation, and the frequency offset estimation using the synchronization preamble, and the cell identification using the cell searching preamble. Performance of each synchronization and cell searching step is analyzed and the analytic results including the overall performance of the synchronization and cell searching are verified by computer simulation. It is shown that the proposed preamble with the corresponding synchronization and cell searching algorithm can provide very robust synchronization and cell searching capability even in bad cellular environments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.99-108
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• 1999

In this paper, we propose $\pi$/4 QPSK scheme with block modulation algorithm, which can reduce preamble in order to transmit ATM cell efficiently in the uplink channel of LMDS, and also designed a new carrier recovery circuit which can improve carrier synchronization performance of block demodulation algorithm. The $\pi$/4 QPSK scheme employing the proposed block modulation algorithm achieved efficient frame transmission by making use of a few preamble when carrier synchronization, symbol timing synchronization and slot timing synchronization were performed by burst data of ATM cell in LMDS environment. For performance evaluation of the proposed method, a simulation analyzing the variation of carrier synchronization, symbol timing synchronization and slot timing synchronization using LMDS environment and burst mode condition was executed. In the simulation, the proposed method showed a good performance even though the reduced preamble as a few aspossible when carrier synchronization, symbol timing synchronization and slot timing synchronization is performed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.5
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• pp.1045-1057
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• 1997

In this paper, we propose an algorithm of block synchronization that uses data withoug synchronization preambles. Block synchronization systems is implemented using the DSP chip employing the proposed algorithm. The data spread of the DFT blocks is proportional to the offset of DFT block and this information is used to achieve the block synchronization in the receiver. The initial bleock synchronization and the clock synchronization between transmitter and receiver are achieved using the early-late removal of the guard interval. The hardware implmentation is carried out using the DSP chip TM320C30 to verify the proposed block synchronization algorithm with the data rate 1200bps. The DSP chip calculates the spread of the 128 complex FFT in the receiver with the system clock 30MHz. It is believed that the proposed synchronization algorithm can be used in the design of OFDM block synchronization with the high processing DSP chip.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.06a
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• pp.246-251
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• 1998

The basic requirement of a distributed multimedia system are intramedia synchronization which asks the strict delay and jitter for the check period of media buffer and the scaling duration with periodic continuous media such as audio and video media, and intermedia synchronization that needs the constraint for relative time relations among them when several media are presented in parallel. In this paper, a distributed multimedia synchronization algorithm based on the fuzzy logic is presented and the performance is evaluated through simulation. Intramedia synchronisation algorithm uses the media scaling techniques and intermedia synchronization algorithm uses variable service rates on the basis of fuzzy logic to solve the multimedia synchronization problem.

• Journal of Communications and Networks
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• v.2 no.1
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• pp.69-75
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• 2000

A new frame synchronization confirmation technique using a pilot pattern of both uplink and downlink channels is proposed for W-CDMA (Wideband Code Division Multiple Access) system. It is shown that by using this technique, we can cancel the side lobe for autocorrelation functions of the frame synchronization words of pilot pattern have the maximum to-of-phase autocorrelation value "4" with two peak values equal in magnitude and opposite in polarity at zero and middle shifts. Due to this side lobe cancellation effect, therefore, the autocorrelation function of the frame synchronization words becomes ideal for the frame synchronization confirmation since double maximum correlation values equal in magnitude and opposite polarity at zero ad middle shifts can be achieved. This property can be used to double check frame synchronization timing and thus. improve the frame synchronization confirmation performance.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.293-300
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• 2009

In this paper, we describe a method for synchronization protocol method used in control system based on network and IEEE 1599 synchronization method which used for implementation of synchronization technology of advanced industrial Ethernet. We also implement and perform the experiment for synchronization technology of EtherCAT communication which is one of the industrial Ethernet technology used IEEE 1599 synchronization technology based on time. And we describe an evaluation for experiment result, improve the problem and future plan.