• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.49-56
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• 2006

This paper describes the design and the verification of IEEE 802.15.4 LR-WPAN 2.4GHz Physical layer for Ubiquitous Sensor Network(USN). We designed the Carrier Frequency Offset(CFO) compensation satisfied the frequency tolerance of IEEE 802.15.4 LR-WPAN and the adaptive matched filter that re-setting of the threshold for the symbol synchronization of the various USN environment. The multiplications is reduced 1/16 by this method each other at i, q phases and has 0.5dB performance improvement in detection probability. Proposed baseband system is designed with verilog HDL and implemented using FPGA prototype board.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.806-813
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• 2009

This paper presents a modem chip design for high-speed wireless communications. Among the high-speed communication technologies, we design the UWB (Ultra-Wideband) modem SoC (System-on-Chip) Chip based on a MB-OFDM scheme which uses wide frequency band and gives low frequency interference to other communication services. The baseband system of the modem SoC chip is designed according to the standard document published by WiMedia. The SoC chip consists of FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform), transmitter, receiver, symbol synchronizer, frequency offset estimator, Viterbi decoder, and other receiving parts. The chip is designed using 90nm CMOS (Complementary Metal-Oxide-Semiconductor) procedure. The chip size is about 5mm x 5mm and was fab-out in July 20th, 2009.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.1-7
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• 2010

A new frequency offset estimation algorithm for chirp spread spectrum based on matched filter is proposed. Generally, the differential phase between successive symbols is used for the conventional frequency offset estimation algorithm. However, if the conventional frequency offset estimation algorithm is used for CSS, phase ambiguity arises because of long symbol duration and guard time. The phase ambiguity causes performance degradation of matched filter since the received signal is corrupted by the integer frequency offset. In this paper, we propose a new frequency offset estimation algorithm which separates integer and fractional frequency offset estimation for removing the phase ambiguity. The proposed algorithm estimates the integer frequency offset by using differential phase between matched filtering results of sub-chirps and successive symbols. Then, the fractional frequency offset is estimated by using the differential phase between successive symbols Simulation results show that the proposed algorithm well removes the phase ambiguity, and have almost same estimation performance compared with conventional one when there is not the phase ambiguity.

• Journal of Navigation and Port Research
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• v.41 no.4
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• pp.173-180
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• 2017

Underwater communications are degraded as a result of inter symbol interference in multipath channels. Therefore, a channel coding scheme is essential for underwater communications. Packets consist of a PN sequence and a data field, and the uncoded PN sequence is used to estimate the frequency and phase offset using a Doppler and phase estimation algorithm. The estimated frequency and phase offset are fed to a coded data field to compensate for the Doppler and phase offset. The PN sequence is generally utilized to acquire the synchronization information, and the bit error rate of an uncoded PN sequence predicts the performance of the coded data field. To ensure few errors, we resort to powerful BCJR decoding algorithms of convolutional codes with rates of 1/2, 2/3, and 3/4. We use this powerful channel coding algorithm to present an efficient receiver structure based on the relation between the bit error of the uncoded PN sequence and coded data field in computer simulations and lake experiments.

• The KIPS Transactions:PartC
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• v.13C no.3 s.106
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• pp.369-374
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• 2006

This paper related with the performance improvement of adaptive equalizer that is a based on the tricepstrum eqalization algorithm by using the received signal. Adaptive equalizer used for the improvement of communication performance, like as high speed, maintain of synchronization, BER, at the receive side in the environment of communication channel of the presence of the aditive noise, phase distortion and frequency selective fading, mainly. It's characteristics are nearly same as the inverse characterstics of the communication channel. In this paper, the TEA algorithm using the HOS and the 16-QAM which is 2-dimensional signaling method for being considered signal was used. For the precoding of 16-QAM singnal in the assignment of the signal costellation, Gray code was used, and the improvement of performance was gained by computer simulation in the residual intersymbol interence and mean squared error which is representive measurement of adaptive equalizer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.9-17
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• 2000

In this paper we implement computer simulation system of 4FSK signal MODEM using Quadrature detector and analyze overall tranceiver system. We follow the FLEX wireless paging system standards and construct premodulation filter and data frame. We propose an efficient open loop symbol timing recovery algorithm which takes advantage of 128 bit length preamble pattern and also propose a 32 bit UW pattern which Is based on the optimal UW detection method, and excellent aperiodic autocorrelation characteristic. The BER simulation in the fading channel as well as AWGN is performed with BCH coding and Interleaving to the Quadrature detector system and it is shown that a high coding fain occurs in the fading channel rather than AWGN channel.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.47-54
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• 2004

The previous works for WLAN system based on OFDM is mainly individual study for independent frequency offset or symbol synchronization. In this paper, the performance of IEEE 802.11a WLAN(Wireless Local Area Network) system in the realistic indoor multipath channel models is analyzed with frequency offset compensation and channel estimation methods. For the performance analysis of the WLAN system indoor Rayleigh multipath channels are adopted, and the BER(Bit Error Rate) of WLAN system is calculated with y2 code-rate 16-QAM based on standard specification. From the simulation results, the difference of required Eb/No for BER of 10-3 is 1-2dB between the channel estimation and frequency offset compensation, and perfect channel estimation and no frequency offset.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10B
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• pp.1150-1158
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• 2011

More than 100 Mbps rate is needed in the UBcN for a subscriber to receive broadband traffics with multi-channel like UDTV or 3DTV. Although the optical fiber is recently deployed for the FTTH, the UTP is the most widely used medium and will be used in UBcN age. Network providers may consider the 1000BASE-T or the vectorized VDSL if they adopts the UTP in the place where does not have optical fibers. But UTP should be expanded because 1000BASE-T and vectorized UTP needs 4 and 3 pairs cable, respectively while residential region has not exceeding 2 pair UTP cable. To solve the problem, we propose a 500BASE-T technology using 2 pairs UTP in this paper. The technology introduces a rate adaptation sublayer and a SERDES sublayer above and under the PCS, respectively. The rate adaptation sublayer is compatible for the GMII. Also, if we modify the SERDES sublayer, the technology can easily obtain 250BASE-T with 2 pairs UTP. We implement such functions with FPGA and analog board and verify the function of rate adaptation and symbol vector synchronization, and effective transmission rate by experiments. In particular, we show that link efficiency is increased by enable control in the rate adaptation sublayer.