• Title/Summary/Keyword: Symbol Timing Recovery

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Efficient Clock Synchronization Schemes for Enhancing Error Performance of OFDM Wireless Multimedia Communication Systems (OFDM 무선 멀티미디어 통신 시스템의 오율성능 향상을 위한 효율적인 샘플링 클럭 동기방식)

  • 김동옥;윤종호
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.1
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    • pp.69-74
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    • 2003
  • In this paper, we propose the synchronization recovery algorithm which is suitable to wireless Multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFTT after the getting the frequency, response of deducted channel from channel deducted of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of ${\pm}$ 1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

A Design of All-Digital QPSK Demodulator for High-Speed Wireless Transmission Systems (고속 무선 전송시스템을 위한 All-Digital QPSK 복조기의 설계)

  • 고성찬;정지원
    • Journal of Korea Society of Industrial Information Systems
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    • v.8 no.1
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    • pp.83-91
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    • 2003
  • High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

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Design of the PHY Structure of a Voice and Data Transceiver with Security (보안성을 갖는 음성 및 데이터 트랜시버의 물리 계층 구조 설계)

  • Eun, Chang-Soo;Lom, Sun-Min;Lee, Kyoung-Min
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.10 s.352
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    • pp.46-54
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    • 2006
  • In this paper, we propose a digital transceiver that can overcome the problems which current analog transceivers have. For the proposed transceiver, we assumed a frequency resource that consists of discrete and narrow channels. We also assumed that person-to-group, group-to-group, as well as person-to-person, voice and data communications with moderate security should be devisedand the data rate is 1 Mbps with simultaneous voice and data. Frequency hewing spread spectrum (FH-SS) and differential 8-PSK (D8PSK) were adopted for security reasons and bandwidth constraints, and for the reduction of implementation complexity, respectively. For the carrier and the symbol timing recovery, the structure of the preamble was proposed based on the IEEE 802.11 FHSS frame format to improve detection probability. The computer simulation results and power budget analysis implies that the proposed system can be usedin simple wireless communications in place of such as analog walkie-talkies.

A Study on the FSK Synchronization and MODEM Techniques for Mobile Communication Part II : Performance Analysis and Design of The FSK MODEM (이동통신을 위한 FSK 동기 및 변복조기술에 관한 연구 II부. FSK 모뎀 설계 및 성능평가)

  • Kim, Gi-Yun;Choe, Hyeong-Jin;Jo, Byeong-Hak
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.3
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    • pp.9-17
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    • 2000
  • In this paper we implement computer simulation system of 4FSK signal MODEM using Quadrature detector and analyze overall tranceiver system. We follow the FLEX wireless paging system standards and construct premodulation filter and data frame. We propose an efficient open loop symbol timing recovery algorithm which takes advantage of 128 bit length preamble pattern and also propose a 32 bit UW pattern which Is based on the optimal UW detection method, and excellent aperiodic autocorrelation characteristic. The BER simulation in the fading channel as well as AWGN is performed with BCH coding and Interleaving to the Quadrature detector system and it is shown that a high coding fain occurs in the fading channel rather than AWGN channel.

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