• Journal of Electrical Engineering and Technology
• /
• v.7 no.5
• /
• pp.714-723
• /
• 2012

A new Z-source inverter (ZSI) topology is developed to improve voltage boost ability. The proposed topology is modified from the switched inductor topology by adding some more inductors and diodes into inductor branch to the conventional Z-source network. The modulation methods developed for the conventional ZSI can be easily utilized in the proposed ZSI. The proposed ZSI has an ability to obtain a higher voltage boost ratio compared with the conventional ZSI under the same shoot-through duty ratio. Since a smaller shoot-through duty ratio is required for high voltage boost, the proposed ZSI is able to reduce the voltage stress on Z-source capacitor and inverter-bridge. Theoretical analysis and operating principle of the proposed topology are explicitly described. In addition, the design guideline of the proposed Z-source network as well as the PWM control method to achieve the desired voltage boost factor is also analyzed in detail. The improved performances are validated by both simulation and experiment.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• v.3B no.1
• /
• pp.37-43
• /
• 2003

This paper proposes a soft-switching current source inverter for a photovoltaic power system. The proposed inverter has an H-type switched-capacitor module composed of two semiconductor switches, two diodes, and an LC resonant circuit. The operation of the proposed system was analyzed by a theoretical approach with equivalent circuits and was verified by computer simulations with SPICE and experimental implementation with a hardware prototype. The proposed system could be effectively applied for the power converter of photovoltaic power system interconnected with the AC power system.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1034-1037
• /
• 2002

A switched-capacitor(SC) type DC-DC converter having capability of integrated circuit fabrication have been marked for the application of mobile equipments. Especially, a ring type SC power supply is featured by the flexible and dynamic voltage conversion ratio change. In this paper, an improvement of the gate driving techniques is proposed for high power efficiency and less area occupation on the chip. Furthermore, its power-saving operation in the stand-by state is proposed. The three-capacitors ring type power supply is really designed and discussed. As results, the simulation results shows the high efficiency of 92.1%, and the higher output put voltage of 10.5 V compared with conventional one of 8.6 V.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.93-96
• /
• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.1
• /
• pp.77-85
• /
• 2009

With the advent of power semiconductor switching devices, power electronics relating to high frequency electromagnetic eddy current based induction heating technology have become more suitable and acceptable. This paper presents high-frequency induction heating cooking appliance circuit based on the zero current switching-PWM single ended push-pull(ZCS-PWM SEPP) resonant inverter added AC-DC converter. This inverter uses pulse-width-modulation(PWM) control method with active auxiliary quasi-resonant lossless inductor snubbers and a switched capacitor. To improved the transient performance, the PI controller is applied for this system. For the systematic parameter optimization of the PI controller, the gradient-based optimization algorithm is applied. The performance of optimized parameters is evaluated using simulation and experimental test. These results show that the proposed systematic optimal tuning method improve the transient performances of this system.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.627-628
• /
• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

• Proceedings of the KIPE Conference
• /
• 2012.07a
• /
• pp.353-354
• /
• 2012

본 논문은 동축권선 변압기를 이용한 승압형 플라이백 컨버터에 절연형 스위치드 커패시터 셀을 추가한 새로운 토폴로지를 제안한다. 제안하는 회로는 절연형 스위치드 커패시터 셀의 출력과 플라이백의 출력을 직렬 연결하여 고승압에 유리하고 스위치 온타임과 스위치 오프타임 모두 전력을 전달하여 기존의 플라이백 컨버터보다 향상된 변압기의 이용률을 가진다. 제안된 회로의 동작원리를 설명하고 60W급 하드웨어 프로토 타입을 이용하여 검증하였다.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.234-240
• /
• 2013

This paper presents an incremental delta-sigma analog-to-digital converter (ADC) for a single-electrode capacitive touch sensor. The second-order cascade of integrators with distributed feedback (CIFB) delta-sigma modulator with 1-bit quantization was fabricated by a $0.18-{\mu}m$ CMOS process. In order to achieve a wide input range in this incremental delta-sigma analog-to-digital converter, the shielding signal and the digitally controlled offset capacitors are used in front of a converter. This circuit operated at a supply voltage of 2.6 V to 3.7 V, and is suitable for single-electrode capacitive touch sensor for ${\pm}10-pF$ input range with sub-fF resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.85-96
• /
• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.48-55
• /
• 1999

This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the AGC in the proposed system is controlled directly by digital bits without conventional extra D/A converters and the signal settling behavior is almost independent of AGC gain variation at video speeds. A capacitor-segment combination technique to obtain large capacitance values considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A proposed layout scheme for capacitor implementation shows AGC matching accuracy better than 0.1 %. The outputs from the AGC are transferred to a 10b A/D converter integrated on the same chip. The proposed AGC is implemented as a sub-block of a CCD camera interface system using a 0.5 um n-well CMOS process. The prototype shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz.