• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.167-174
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• 2003

This paper proposes a network processor especially optimized for content switching. With 2Gbps port capability, it integrates packet processor cluster, content-based classification engine and traffic manager on a single chip. A switch fabric architecture is also designed for scale-up of the network processor's capability over hundreds gigabit bandwidth. Applied in real network systems, the network processor shows wire-speed network address translator (NAT) and content-based switching performance.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.137-140
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• 1991

The TDX-10 Time Switch architecture has modularity, high reliability and considerable large switch fabric having separated and both-way 1K time slot interchange switching circuit elements. In this paper, we present key functions, architecture, features and traffic characteristic of TDX-10 Time Switch. And we also describe some basic implementation technologies such as Frame Base Read-Write Separation Method, Multi-Write Method and Read-Write Separation Technique with Dual-port Memory.

• Fashion & Textile Research Journal
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• v.18 no.3
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• pp.363-373
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• 2016

This study aims to develop an all-fabric integrated smart jacket in order to create a temperature-regulating system based on a user experience design. For this research, previous research technologies of a textile switch interface and a temperature-regulating system were utilized and a unifying technology for the all-fabric integrated smart jacket was developed which can provide the appropriate temperature environments to the human body. A self-heating textile was applied at the areas of the back and hood in the final tested jacket, and an embroidery circuit was developed in the form of a rectangle in the back and in both ears of the hood, taking into account the pattern of the jacket part where it was be applied and the embroidery production method. The textile switch interface was designed in a three-layer structure: an embroidery circuit line in a conductive yarn, an interval material, and a conductive sensing material, and it was made to work with the input and output sensors through the multiple input method. After the all-fabric integrated smart jacket was produced according to the pattern, all of the textile band lines for transmission were gathered and connected with a miniature module for controlling temperature and then integrated into the inside of the left chest pocket of the jacket. After the users put on this jacket, they were asked to assess the wearing satisfaction. Most of them reported a very low level of irritation and discomfort and said that the jacket was as comfortable as everyday clothing.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.123-132
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• 2005

In this Paper, we present an improvement of switch node for wavelength multiplex optical network. Currently because of quick increase of internet traffic a big network capacity is demanded. Wavelength multiplex optical network Provides the data transfer of high speed and the transparent characteristic of the data. Therefore optic network configuration is the most powerful technology in the future. It will be able to control the massive traffic from the optical network in order to transmit the multimedia information of very many quantify. Consequently the node where the traffic control is Possible, is demanded. The optical switch node which manages efficiently the multiple wavelength was Proposed. This switch is composed of a optical switch module for switching and a wavelength converter module for wavelength conversion. It will be able to compose the switch fabric without optical/electro or electro/optical conversion using optical MEMS(Micro Electro Mechanical Switches) module. Finally, we present the good test result regarding the operational qualify of the switch fabric and the performance of optical signal from the switch node. The proposed switch node of the optic network will be able to control the massive traffic with all optical.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.11
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• pp.1143-1153
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• 1991

In this paper, we proposed a new ATM switch structure which is based on the GAMMA network, proving multipath between an input and an output port. The size of the proposed new ATM switch will be smaller than the switches based on the BANYAN network, which includes the Sorting network to resolve the blocking in the switch fabric. Also, the validity and the utility of the proposed switch structure is verified through a simulation method.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.523-530
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• 2016

We use both theoretical analysis and simulations to study the impact of crosspoint-queued (CQ) buffer size on CQ switch throughput and delay performance under different traffic models, input loads, and scheduling algorithms. In this paper, we present the following. 1) We prove the stability of CQ switch using any work-conserving scheduling algorithm. 2) We present an exact closed-form formula for the CQ switch throughput and a non-closed-form but convergent formula for its delay using static non-work-conserving random scheduling algorithms with any given buffer size under independent Bernoulli traffic. 3) We show that the above results can serve as a conservative guide on deciding the required buffer size in pure CQ switches using work-conserving algorithms such as the random scheduling, under independent Bernoulli traffic. 4) Furthermore, our simulation results under real-trace traffic show that simple round-robin and random work-conserving algorithms can achieve quite good throughput and delay performance with a feasible crosspoint buffer size. Our work reveals the impact of buffer size on the CQ switch performance and provides a theoretical guide on designing the buffer size in pure CQ switch, which is an important step toward building ultra-high-speed switch fabrics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.3
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• pp.12-23
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• 1997

In this paper, we propose a new cell switch fabric for increasing the performance of ATM switching systems. Proposed switching network consists of a sorting network and a routing network. Both of these are multistage networks where each stage performs a fixed permutation on the incoming lines, and then routes them through a clumn of 2x2 switching elements. It is designed for distributing inputs and parallel processing to reduce the hardware complexity and obtain high performance of switching network. The structure and the operation of th eswitching network aredescribed and the performanceof the switching network is anlyzed under uniform traffic models. In this result, though the size of proposed network is increased the large scale, it has always the same throughput as the that of genral output queueing system with N=2. So, it is found that our proposed network is appropriate for the high apeed and lrger size of ATM switching systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.394-397
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• 2003

In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.252-257
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• 1998

본 논문은 입력 버퍼링 구조를 갖는 패킷 스위치에서 입력 확장 스위치 패브릭 구조를 통한 성능 개선에 관한 연구이다. 스위치 패브릭의 처리 능력 개선을 위한 다양한 구조에 대한 성능 및 설계 파라메터를 분석하고, 목적지별로 구분되는 입력 확장스위치 패브릭 구조를 제안하고 버스트 트래픽 환경에서 제안된 스위치의 성능을 분석한다.