• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.775-777
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• 2000

본 논문에서는 buffer를 장착한 양 방향성 $a{\times}b$ switch들로 구성된 fat-tree network의 성능 분석 기법을 제안하고, 분석 모형의 타당성을 검증하였다. 제안한 분석 기법은 먼저 스위치 내부의 데이터 이동 패턴을 확률식으로 표현하고. 나아가서 buffer를 장착한 $a{\times}b$ switch의 buffer 크기에 따른 정상상태 throughput을 간단한 수식으로 구할 수 있도록 하였다. 이를 토대로 buffer를 장착한 $a{\times}b$ switch로 구성된 fat-tree network의 성능을 분석하고, 제안한 분석모형의 실효성 입증을 위하여 simulation을 시행한 후 결과를 비교 분석하였다.

• Journal of Communications and Networks
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• v.5 no.1
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• pp.82-89
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• 2003

In this paper, an efficient threshold-based filtering (TF) buffer management scheme is proposed. The TF is capable of minimizing the overall loss performance and improving the fairness of buffer usage in a shared buffer packet switch. The TF consists of two mechanisms. One mechanism is to classify the output ports as sctive or inactive by comparing their queue lengths with a dedicated buffer allocation factor. The other mechanism is to filter the arrival packets of inactive output ports when the total queue length exceeds a threshold value. A theoretical queuing model of TF is formulated and resolved for the overall packet loss probability. Computer simulations are used to compare the overall loss performance of TF, dynamic threshold (DT), static threshold (ST) and pushout (PO). We find that TF scheme is more robust against dynamic traffic variations than DT and ST. Also, although the over-all loss performance between TF and PO are close to each other, the implementation of TF is much simpler than the PO.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• The Journal of the Korea Contents Association
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• v.2 no.2
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• pp.73-84
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• 2002

In this paper, we propose a enhanced ERICA switch algorithm using the buffer management scheme which can reduce the queue length, support the efficiency link utilization and the fair share. It has three different buffer thresholds which are low threshold, congestion notification threshold and high threshold. According to the each buffer threshold status, switch announced congestion notification to the source differently. So, sources could know the congestion more quickly and fast remover from network congestion. As a experimental results, it is proved that proposed algorithm is the more efficient than ERICA. Especially, proposed switch algorithm provides congestion control mechanism to make the best use of with keeping fairness and reduce queue length.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.394-397
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• 2003

In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.119-130
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• 1996

This paper is the part I of the full study about improved structure of fully interconnected ATM switch to develop the small sized switch element and practical implemention of switch network. This part I paper describes about proposed switch structure, performance evaluations and some of considerations to practical implementation. The proposed structure is constructed of two step buffering scheme in a filtered multiplexer. First step buffering is carried out by small sized dedicated buffers located at each input port. And second step buffering is provided by a large sized common buffer at the output port. To control bursty traffic, we use speed up factor in multiplexing and priority polling according to the levels of buffer occupancy. Proposed structure was evaluated by computer simulation with two evaluation points. One is comparision of multiplexing discipline between hub polling and priority polling. The ogher is overall which should be considered to improve the practical implementation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.1209-1218
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• 1995

In this paper, we develope an ATM switch simulator in order to evaluate the HAN/B-ISDN ATM switch currently being developed by ETRI. It models the basic cell switching functions of the target ATM switch with priority control and multicasting features and it also supports such various traffic models as random or bursty traffic, balanced or unbalanced traffic, multicast traffic models. Using this simulator, we can evaluate the performances of the ATM switch in terms of various performance indices, i.e. cell delay, cell loss probability, etc., and this simulator can be utilized in the system parameter tunings such as the common buffer size and address buffer size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.629-642
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• 1996

ATM switch handles the traffic for a wide range of appliations with different QOS(Quality-of-Service) requirements. In ATM switch, the priority control mechanism is needed to improve effectively the required QOS requirements. In this paper, we propose a priority control mechanism using the cell transfer ratio type and discard threshold in order to archive the cell loss probability requirement and the delay requirement of each service class. The service classes of our concern are the service class with high time priority(class 1) and the service class with high loss priority control mechanism, cells for two kind of service classes are stored and processed within one buffer. In case cells are stored in the buffer, cells for class 2 are allocated in the stored and processed within one buffer. In case cells are stored in the buffer, cells for class 2 are allocated in the shole range of the buffer and cells for class 1 are allocated up to discard threshold of the buffer. In case cells in the buffer are transmitted, one cell for class 1 is transmitted whenever the maximum K cells for class 2 are transmitted consecutively. We analyze the time delay and the loss probability for each class of traffic using Markov chain. The results show that the characteristics of the mean cell delay about cells for class 1 becomes better and that of the cell loss probability about cells for class 2 becomes better by selecting properly discard threshold of the buffer and the cell transfer ratio according to the condition of input traffic.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4B
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• pp.162-169
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• 2005

Network traffic measurements show that the data traffic on packet switched networks has the self-similar features which is different from the traditional traffic models such as Poisson distribution or Markovian process model. Most of the call admission control researches have been done on the performance analysis of a single network switch. It is necessary to consider the performance analysis of the proposed admission control scheme under interconnected switch environment because the data traffic transmits through switches in networks. From the simulation results, it is shown that the call admission control scheme may not operate properly on the interconnected switch even though the scheme works well on a single switch. In this parer, we analyze the cell loss probability, utilization and self-similarity of output ports of the interconnected networks switch by using shared buffer memory management schemes and propose the new call admission control scheme considering the interconnected network switches under self-similar traffic environments.