• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.14-24
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• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.

• The Korean Journal of Physiology
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• v.1 no.1
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• pp.121-130
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• 1967

Determination of weekly and daily energy expenditure was made on 62 Republic of Korea Army cadets who were selected at random in order to estimate the weekly and daily ealorie expenditure. Basal metabolic rate (B.M.R.), and energy cost of various military and daily activities were measured by indirect calorimetry using open circuit method. Time-motion studies were also carried on using a stop-watch. The total weekly energy expenditure was calculated by summation of data using energy cost per minute, and the time spent on each activity. Determination of daily energy expenditure was deduced from each data of weekly energy expenditure. Food survey was also carried on for a week, and daily calorie intake was determined by a weekly average discounting loss in cooking. All measurements were determined from the Standard Table of Food Composition published by the Ministry of National Defense (1961). Following data were observed. 1. Physical status of cadets are as follows. Please note that the height and weight averages are 1-2cm and 4-5kg respectively over that of the Seoul National University students. First year Height 167.92 cm $(S.D.{\pm}4.09)$ Weight 61.72 kg $(S.D.{\pm}4.53)$ Second year Height 167.89 cm $(S.D.{\pm}3.46)$ Weight 63.01 kg $(S.D.{\pm}4.61)$ Third year Height 168.15 cm $(S.D.{\pm}4.24)$ Weight 43.48 kg $(S.D.{\pm}5.03)$ Fourth year Height 168.10 cm $(S.D.{\pm}3.70)$ Weight 64.02kg $(S.D.{\pm}5.10)$ 2. The B.M.R. of cadets averaged $36.57\;Cal./m^2/hr.(S.D.{\pm}3.63\;Cal./m^2/hr.)$ is almost equal with data on the same ages of civilians and the Japanese, but a lower average of $5.1\;Cal./m^2/hr.$ than that of a common soldier. 3. The energy expenditure during various military activities is close agreement with Consolazio. Passmore and Durnin, and Japanese reports.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.145-151
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• 2004

For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.641-647
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• 2011

This paper describes a design and fabrication of SDLVA. The SDLVA operates 0.5~2.0 GHz with -70~0 dBm dynamic range. The SDLVA is consisted of 5-stage RF block, 2-stage detector block and summation circuit using clamping op-amp to improve video linearity. The result of measure, SDLVA of RF path has over 73 dB small-signal gain and 10.1~12.2 dBm saturation power. The video path has 25 mV/ dB${\pm}$1.0 mV and under ${\pm}$1.5 dB video linearity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.979-986
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• 2013

In this paper, a TVS diode which is commonly used as a ESD protector in wireless communication devices could cause antenna wireless sensitivity to decrease has been analyzed. When a smartphone doesn't have enough space to place many components, there would be its speaker near antenna area. In order to protect ESD coming through the speaker there also could be a TVS within antenna GND area. Digital audio signal which was sent to speaker and CDMA RF communication signal coupled from antenna was mixed by TVS. And this leakage current running through TVS resulted in decrease of antenna wireless sensitivity. The results of various experiments can be explained using circuit simulation. Following works will give us some insights that can reduce unwanted summation of digital and RF signal due to nonlinearity of ESD protectors.