• Journal of IKEEE
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• v.18 no.3
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• pp.392-397
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• 2014

In this paper, we propose a memory operation system architecture for memory latency penalty reduction in SIMT architecture based stream processor. The proposed architecture applied non-blocking cache architecture to reduce cache miss penalty generated by blocking cache architecture. We verified that the proposed memory operation architecture improve the performance of the stream processor by comparing processing performances of various algorithms. We measured the performance improvement rate that was improved in accordance with the ratio of memory instruction in each algorithm. As a result, we confirmed that the performance of stream processor improves up to minimum 8.2% and maximum 46.5%.

• Journal of IKEEE
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• v.21 no.1
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• pp.77-80
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• 2017

In this paper, we proposed a way to improve performance of GP-GPU by deletion of superscalar issue from its original form. At first, we simplified the structure of stream processor in order to eliminate superscalar issue. Under this condition, preservation of hardware size and increasing of thread number were followed by functional improvement of GP-GPU. As the number of thread was getting larger, we proposed the new model of warp scheduler which adjusts the group of thread. This superscalar issue-deleted warp scheduler transferred the instructions to warp which was activated by Round Robin Scheduling. Performance comparison was conducted by Gaussian filtering and the results indicated that our newly designed GP-GPU showing 7.89 times better in its performance than original one.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.682-685
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• 2002

In this paper, we defined necessary operations and functional blocks of a multiplexer for 3-D video systems and present our multiplexer design. We adopted the ITU-T's recommendation(H.222.0) to define the operations and functions of the multiplexer and explained the data structures and details of the design for multiview image processing. The data structure of TS(Transport Stream) and PES (Packetized Elementary Stream) in ITU-T Recommendation H.222.0 does not fit our multiview image processing system, because this recommendation is fur wide scope of transmission of non-telephone signals. Therefore, we modified these TS and PES stream structures. The TS is modified to DSS(3D System Stream) and PES is modified to SPDU(DSS Program Data Unit). We constructed the multiplexer through these modified DSS and SPDU. The number of multiview image channels is nine, and the image class employed is MPEG-2 SD(Standard Definition) level which requires a bandwidth of 2∼6 Mbps. The required clock speed should be faster than 54(= 6 ${\times}$ 9)㎒ which is the outer interface clock speed. The inside part of the multiplexer requires a clock speed of only 1/8 of 54㎒, since the inside part of the multiplexer operates by the unit of byte. we used ALTERA Quartus II and the FPGA verification for the simulation.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.278-280
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• 2007

In this paper, wd design the Program Specific Information (PSI) parser and its On-Screen Display (OSD) on the middleware of ALi M3330 MPEG-2 decoder processor to analyze DVB-T Transport Stream(TS) information. To test the functional operation of the designed parser, we implement the DVB-T test board including the RF-tuner using ALi M3330 MPEP-2 decoder processor and confirm the correct operation using the input TS stream generated by DVB-T stream generator. The developed PSI parser could be used for the test environment, various channel extension, and the development of DVB-T reception module.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.169-171
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• 2007

This paper presents the development of DVB-T reception module including the RF-tuner. For the development of the reception module, we design the board using the ALi M3330 MPEG-2 decoder processor and implement its device driver. Simple On-Screen Display (OSD) applications are also designed on the middleware of ALi M3330 MPEG-2 decoder processor. To evaluate the performance of reception module, we test the decoding operations using the input TS stream generated by DVB-T stream generator and confirm the correctness of its functional operations.

• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.259-267
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• 2003

In this paper, we propose a media processor to provide interactive services in mobile multimedia broadcasting environments. The proposed system Is designed to support various functionalities, such as generation of MPEG-4 IOD (Initial Object Descriptor)/OD(Object Descriptor)/BIFS (Binary Format for Scene) data, encapsulation of MPEG-4 AVC (Advanced Video Coding)/BSAC (Bit Sliced Arithmetic Coding) stream and generated IOD/OD/BIFS data into SL (Sync Layer) packet, packetization of SL packet into TS (Transport Stream) packet and multiplexing. The proposed media processor can provide MPEG-4 based interactive services for users.

• Journal of IKEEE
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• v.21 no.1
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• pp.92-95
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• 2017

In this paper, we proposed a way to improve function of small scale GP-GPU. Instead of using superscalar which increase scheduling-complexity, we suggested the application of simple core to maximize GP-GPU performance. Our studies also demonstrated that simplified Stream Processor is one of the way to achieve functional improvement in GP-GPU. In addition, we found that developing of optimal thread-assigning method in Warp Scheduler for specific application improves functional performance of GP-GPU. For examination of GP-GPU functional performance, we suggested the thread-assigning way which coordinated with Deep-Learning system; a part of Neural Network. As a result, we found that functional index in algorithm of Neural Network was increased to 90%, 98% compared with Intel CPU and ARM cortex-A15 4 core respectively.

• Magazine of the Korean Society of Agricultural Engineers
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• v.39 no.2
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• pp.103-112
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• 1997

A CELTHYM(CEll-based Long-term HYdrologic Model), a pre-processor and a post-processor that can he integrated with geographic information system(GIS) were developed to predict the stream flow of a small agricultural watershed. Three kinds of routines, that are watershed boundary extraction routine(WBER), curve number calculation routine(CNR) and maximum available soil moisture calculation routine(MASR) composed pre-processor that was nicely interfaced with CELTRYM and GIS. Two kinds of routines, grapher and map composer composed post-processor that was well adapted CELTHYM output to chart making and GIS map making. The developed pre-post processor was useful for the GIS integration and spatial comprehension of the CELTHYM output.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.49-56
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• 1994

This paper describes the design principles and methods of electronic processor for thermal imager with the SPRITE detector, operating in the 8-12 micron band. The thermal imager consists of a optical scanner containing the detector and an electrical signal processor. The optical scanner utilizing rotating polygon and oscillating mirror, is 2-dimensional serial/parallel scan type using 5 elements of the detector. And the electronic processor has pre-processing of 5 chnanel's thermal signal from the detector, and performs digital scan conversion to reform the parallel data stream into serial analog data compatible with conventional RS-170 video. Through the designed electronic processor, we have acquired a satisfactory thermal image. And the MRTD (Minimum Resolvable Temperature Difference) is 0.5$^{\circ}$K at 7.5 cycles/mm.