• 제목/요약/키워드: Stage Matching

검색결과 320건 처리시간 0.021초

동공의 반사특징을 이용한 얼굴위조판별 시스템 (Fake Face Detection System Using Pupil Reflection)

  • 양재준;조성원;정선태
    • 한국지능시스템학회논문지
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    • 제20권5호
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    • pp.645-651
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    • 2010
  • 최근 지능형 범죄가 늘면서 첨단 보안 기술에 대한 요구가 점차 늘어나고 있다. 현재까지 보고된 위조영상검출방법은 실용화를 위하여 정확도 개선이 요구된다. 본 논문에서는 사람의 얼굴에 대하여 동공의 반사광을 이용한 얼굴위조판별 시스템을 제안한다. 제안된 시스템은 먼저 다중 스케일 가버특징 벡터를 기반으로 눈의 위치를 찾은 후 2단계의 템플릿 매칭을 통해서 설정된 적용범위를 벗어나는 눈에 대하여 위조판별을 고려하지 않음으로써 정확도를 높이는 방법을 사용한다. 신뢰도가 확보된 눈의 위치를 기반으로 적외선 조명에 반사되는 동공의 특징을 이용하여 눈위치 근처에서의 화소값을 계산하여 위조 여부를 판단한다. 실험을 통하여 본 논문에서 제안한 방법이 더욱 신뢰성 높은 위조판별시스템임을 확인하였다.

고효율 및 높은 격리 특성을 갖는 Ka 대역 도파관 결합기 설계 및 제작 (Design and Fabrication of Ka-band Waveguide Combiner with High Efficiency and High Isolation Characteristics)

  • 김효철;조흥래;이주흔;이덕재;안세환;이만희;주지한;김홍락
    • 한국인터넷방송통신학회논문지
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    • 제22권2호
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    • pp.35-42
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    • 2022
  • 본 논문에서는 SSPA(Solid state amplifier) 의 핵심 모듈인 결합기의 효율 및 격리 특성을 높이는 방법에 대해 연구하였다. 구체적으로 도파관 결합기에서 공용 포트와 격리 포트 정합을 이루어 격리도를 확보 하였다. 정합을 위한 매칭 구조는 원형 디스크 형태로 도파관 결합기 내부에서 음각으로 가공하게 된다. 구조는 매우 단순하여 안정적인 성능 확보가 가능하다. 그리고 이러한 구조는 이전 연구 대비 60배 이상의 높은 임계전력 성능을 보여 고출력에 적합함을 확인하였다. 그리고 1단의 T-junction과 2, 3단의 MagicT 결합기를 조합하여 소형화를 이루고, 삽입손실을 줄여 결합 효율을 최적화 하였다. 제작된 도파관 결합기는 16dB 이상의 격리도와 86.2% 의 결합 효율을 얻었다.

제 2형 당뇨 환자의 운동행위 변화단계에 따른 변화과정, 의사결정균형 및 자기 효능감에 관한 연구 (Process of Change, Decisional Balance and Self-Efficacy Corresponding to the Stage of Exercise Behavior in Patients with Type 2 Diabetes Mellitus)

  • 김춘자
    • 성인간호학회지
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    • 제14권1호
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    • pp.83-92
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    • 2002
  • Purpose: This study was performed to identify the process of change, decisional balance and self-efficacy corresponding to the stage of exercise behavior using Transtheoretical Model in patients with type 2 diabetes mellitus. Method: The study method was a survey in 100 type 2 DM patients at out-patients clinic of Y medical center from March 19, 2000 to October 30, 2000. Result: The results were as follows: The subjects were divided into five stages of exercise behavior ; 15.0% in pre-contemplation stage, 33.0% in contemplation stage, 17.0% in preparation stage, 16.0% in action stage and 19.0% in maintenance stage. The subjects in pre-contemplation stage used all processes of change in the least. "Dramatic relief(DR)", "Environmental reevaluation(ER)" and "Self reevaluation(SR)" were identified as main processes of change in contemplation stage. "Consciousness raising(CR)", "DR" were used higher than average in preparation stage. Helping relationships(HR)", "CR", "ER", "SR", "Social liberation(SL)", "Counter conditioning (CC)", "Reinforcement management(RM)", "Self iberation(SEL)" and "Stimulus control(SC)" were used higher than average in action stage. The subjects in maintenance stage used all process of change the highest except "DR"and "HR". "Cons" score of decisional balance was the highest in pre-contemplation stage, "Pros" score was the highest in action stage and "Self-efficacy" score was the highest in maintenance stage. Conclusion: This study can provide the basis of staged matching exercise program using TTM for more effective and useful intervention.

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ICT 활용 교육을 위한 원격지 학급간 협동 학습 시스템 (Development of a Remote Cooperative Studying System for ICT Using Education)

  • 정영식;이영현;김홍래;김명렬
    • 컴퓨터교육학회논문지
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    • 제5권2호
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    • pp.101-109
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    • 2002
  • 인터넷을 기반으로 한 원격지 학급간 협동 학습 시스템은 원격지 학급을 연결하는 매칭 시스템, 다양한 보상 체계와 상호 작용으로 실질적인 협동 학습이 이루어질 수 있도록 한 커뮤니티 시스템, 개인이나 모둠 및 학습실의 학습 성취도를 평가하고 학습 결과물을 공유할 수 있는 리포트 시스템으로 구성하였다. 특히 협동 학습 과정을 사전 준비 단계, 모둠 구성 단계, 상호 작용 단계, 결과 협의 단계, 평가 정리 단계로 구분하여 시스템에 적용시켰다. 이 시스템은 다양한 상호 작용과 책임 있는 모둠 활동을 제공하므로 교사는 자연스럽게 ICT 활용 교육에 자신감을 갖게 되고, 학생은 정보화 사회에 필요한 기초적인 ICT와 공동체 의식 습득할 것이다.

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Ultra-small Form-Factor Helix on Pad-Type Stage-Bypass WCDMA Tx Power Amplifier Using a Chip-Stacking Technique and a Multilayer Substrate

  • Yoo, Chang-Hyun;Kim, Jung-Hyun
    • ETRI Journal
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    • 제32권2호
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    • pp.327-329
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    • 2010
  • A fully integrated small form-factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix-on-pad integrated passive device output matching, a chip-stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm ${\times}$ 2.2 mm. A stage-bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.

OTA를 이용한 단전원 구동 펄스폭 변조(Pulse Width Modulation) 회로 설계 (Design of PWM(Pulse Width Modulation) Circuit Using OTA with a single-voltage supply)

  • 박선웅;김희준;송재훈;이은진
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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    • pp.2843-2846
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    • 2003
  • This paper proposes a PWM(Pulse Width Modulation) circuit using CMOS OTA with a single-voltage supply. The OTA employed has an input stage which consists of a pair of two MOSFETs operating in plural operation regions. The MOSFETs work complemetarily and realize a rail-to-rail input range. The input stage requires no matching of an n-channel type input circuit and a p-channel type input circuit unlike conventional rail-to-rail input stages because the input stage is realized by single channel type MOSFETs. In order to confirm the validity of the proposed circuit, it is simulated by H-SPICE program. Futhermore, the proposed circuit will be integrated on chip using 0.35 $\mu\textrm{m}$ CMOS technology.

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24GHz 2단 저잡음 증폭기의 설계 및 제작 (Design and Fabrication of two-stage Low Noise Amplifier for 24GHz)

  • 조현식;박창현;김장구;강상록;한석균;최병하
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2003년도 추계종합학술대회
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    • pp.304-308
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    • 2003
  • 본 논문에서는 24GHz에서 동작하는 2단 저잡음 증폭기를 설계 및 제작하였다. 소자는 NEC사의 NE450284C HT-FET를 사용하였고, 양호한 잡음지수를 위한 정합회로 설계 시 좋지 않은 입력 정재 파비를 동시에 고려하여, 원하는 잡음지수와 입력 정재파비를 얻도록 설계하였다. 측정 결과 이득은 16.6dB, 입력 정재파비는 1.6, 그리고 출력 정재파비는 1.5를 넘지 않는 특성을 얻었다.

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지문 Pattern 인식 Algorithm (Fingerprint Pattern Recognition Algorithm)

  • 김정규;김봉일
    • 대한원격탐사학회지
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    • 제3권1호
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    • pp.25-39
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    • 1987
  • The purpose of this research is to develop the Automatic Fingerprint Verfication System by digital computer based on specially in PC level. Fingerprint is used as means of personal identity verification in view of that it has the high reliability and safety. Fingerprint pattern recognition algorithm is constitute of 3 stages, namely of the preprocessing, the feature extraction and the recognition. The preprocessing stage includes smoothing, binarization, thinning and restoration. The feature extraction stage includes the extraction of minutiae and its features. The recognition stage includes the registration and the matching score calculation which measures the similarity between two images. Tests for this study with 325 pairs of fingerprint resulted in 100% of separation which which in turn is turned out to be the reliability of this algorithm.

High-throughput and low-area implementation of orthogonal matching pursuit algorithm for compressive sensing reconstruction

  • Nguyen, Vu Quan;Son, Woo Hyun;Parfieniuk, Marek;Trung, Luong Tran Nhat;Park, Sang Yoon
    • ETRI Journal
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    • 제42권3호
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    • pp.376-387
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    • 2020
  • Massive computation of the reconstruction algorithm for compressive sensing (CS) has been a major concern for its real-time application. In this paper, we propose a novel high-speed architecture for the orthogonal matching pursuit (OMP) algorithm, which is the most frequently used to reconstruct compressively sensed signals. The proposed design offers a very high throughput and includes an innovative pipeline architecture and scheduling algorithm. Least-squares problem solving, which requires a huge amount of computations in the OMP, is implemented by using systolic arrays with four new processing elements. In addition, a distributed-arithmetic-based circuit for matrix multiplication is proposed to counterbalance the area overhead caused by the multi-stage pipelining. The results of logic synthesis show that the proposed design reconstructs signals nearly 19 times faster while occupying an only 1.06 times larger area than the existing designs for N = 256, M = 64, and m = 16, where N is the number of the original samples, M is the length of the measurement vector, and m is the sparsity level of the signal.

A Multi-Stage Approach to Secure Digital Image Search over Public Cloud using Speeded-Up Robust Features (SURF) Algorithm

  • AL-Omari, Ahmad H.;Otair, Mohammed A.;Alzwahreh, Bayan N.
    • International Journal of Computer Science & Network Security
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    • 제21권12호
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    • pp.65-74
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    • 2021
  • Digital image processing and retrieving have increasingly become very popular on the Internet and getting more attention from various multimedia fields. That results in additional privacy requirements placed on efficient image matching techniques in various applications. Hence, several searching methods have been developed when confidential images are used in image matching between pairs of security agencies, most of these search methods either limited by its cost or precision. This study proposes a secure and efficient method that preserves image privacy and confidentially between two communicating parties. To retrieve an image, feature vector is extracted from the given query image, and then the similarities with the stored database images features vector are calculated to retrieve the matched images based on an indexing scheme and matching strategy. We used a secure content-based image retrieval features detector algorithm called Speeded-Up Robust Features (SURF) algorithm over public cloud to extract the features and the Honey Encryption algorithm. The purpose of using the encrypted images database is to provide an accurate searching through encrypted documents without needing decryption. Progress in this area helps protect the privacy of sensitive data stored on the cloud. The experimental results (conducted on a well-known image-set) show that the performance of the proposed methodology achieved a noticeable enhancement level in terms of precision, recall, F-Measure, and execution time.