• Title/Summary/Keyword: Stacked-FET

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Current Sensing Trench Gate Power MOSFET for Motor Driver Applications (모터구동 회로 응용을 위한 대전력 전류 센싱 트렌치 게이트 MOSFET)

  • Kim, Sang-Gi;Park, Hoon-Soo;Won, Jong-Il;Koo, Jin-Gun;Roh, Tae-Moon;Yang, Yil-Suk;Park, Jong-Moon
    • Journal of IKEEE
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    • v.20 no.3
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    • pp.220-225
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    • 2016
  • In this paer, low on-resistance and high-power trench gate MOSFET (Metal-Oxide-Silicon Field Effect Transistor) incorporating current sensing FET (Field Effect Transistor) is proposed and evaluated. The trench gate power MOSFET was fabricated with $0.6{\mu}m$ trench width and $3.0{\mu}m$ cell pitch. Compared with the main switching MOSFET, the on-chip current sensing FET has the same device structure and geometry. In order to improve cell density and device reliability, self-aligned trench etching and hydrogen annealing techniques were performed. Moreover, maintaining low threshold voltage and simultaneously improving gate oxide relialility, the stacked gate oxide structure combining thermal and CVD (chemical vapor deposition) oxides was adopted. The on-resistance and breakdown voltage of the high density trench gate device were evaluated $24m{\Omega}$ and 100 V, respectively. The measured current sensing ratio and it's variation depending on the gate voltage were approximately 70:1 and less than 5.6 %.

Design and Fabrication of Low Loss, High Power SP6T Switch Chips for Quad-Band Applications Using pHEMT Process (pHEMT 공정을 이용한 저손실, 고전력 4중 대역용 SP6T 스위치 칩의 설계 및 제작)

  • Kwon, Tae-Min;Park, Yong-Min;Kim, Dong-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.6
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    • pp.584-597
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    • 2011
  • In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.