• Journal of Power Electronics
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• 제19권6호
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• pp.1449-1457
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• 2019

This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.