• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제16권2호
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• pp.177-185
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• 2010

광선-다각형 교차 계산은 광선 추적법 계산의 상당 부분을 차지하는 중요한 구성요소로서, 보편적으로 정적인 장면에 대해서는 kd-트리와 같은 공간 자료구조를 사용하여 교차 계산을 가속하여왔다. 최근 CPU에 비해 상대적으로 제한된 계산구조를 가지는 GPU에 적합하도록 변형된 kd-트리 탐색 기법이 몇 가지 제시되어 왔는데, 본 논문에서는 이러한 기존 방법을 보완할 수 있는 두 가지 구현 기법을 제안한다. 첫째, 트리 탐색을 위한 스택을 전역 메모리에 할당할 경우 전역 메모리 접근으로 인한 비용을 줄이고자 하는 캐쉬 적용 스택 방법과 둘째, 기존의 로프 방법의 문제점인 상당한 메모리 요구량을 줄이고자 하는 적은 깊이의 스택(short stack)을 사용한 로프 방법을 제시한다. 제안된 방법의 효용성을 보이기 위하여 기존의 GPU용 탐색 방법과의 성능 비교 분석을 수행한다. 이러한 실험 결과는 향후 GPU용 광선추적법 소프트웨어 개발자들이 상황에 맞는 적절한 kd-트리 탐색 방법을 선택할 수 있도록 해주는 중요한 정보를 제공하게 될 것이다.

• 한국항행학회논문지
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• 제12권5호
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• pp.420-428
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• 2008

이 논문에서는 무선랜 대역에 사용가능한 마이크로스트립 형태의 적층 구조 패치안테나를 설계 및 제작 하였다. 복사패치 및 접지면은 PEC(Perfect electronics conductor) 완전 전기도체를 의미하는 금속으로 두께 0.5mm인 도체를 사용하였다. 안테나의 대역폭과 이득을 개선하기 위해서 직사각형 패치를 적층하여 프로브 급전방식으로 급전시켰다. 제작된 적충형 마이크로스트립 패치 안테나는 5 [GHz] 대역에서 VSWR 2:1인 범위가 5100 MHz ~ 6140 MHz 까지 약 l040 MHz의 광대역 특성을 보였고, 안테나 이득은 13 [dBi] 그리고 3dB 빔폭은 약 $40^{\circ}$라는 양호한 시뮬레이션 결과를 얻을 수 있었다.

• 한국재료학회지
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• 제23권3호
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• pp.206-210
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• 2013

In the segmented-in-series solid-oxide fuel cells (SIS-SOFCs), fabrication techniques which use decalcomania paper have many advantages, i.e., an increased active area of the electrode; better interfacial adhesion property between the anode, electrolyte and cathode; and improved layer thickness uniformity. In this work, a cell-stack was fabricated on porous ceramic flattened tube supports using decalcomania paper, which consists of an anode, electrolyte, and a cathode. The anode layer was $40{\mu}m$ thick, and was porous. The electrolyte layers exhibited a uniform thickness of about $20{\mu}m$ with a dense structure. Interfacial adhesion was improved due to the dense structure. The cathode layers was $30{\mu}m$ thick with porous structure, good adhesion to the electrolyte. The ohmic resistance levels at 800, 750 and $700^{\circ}C$ were measured, showing values of 1.49, 1.58 and $1.65{\Omega}{\cdot}cm^2$, respectively. The polarization resistances at 800, 750 and $700^{\circ}C$ were measured to be 1.63, 2.61 and $4.17cm^2$, respectively. These lower resistance values originated from the excellent interfacial adhesion between the anode, electrolyte and cathode. In a two-cell-stack SOFC, open-circuit voltages(OCVs) of 1.915, 1.942 and 1.957 V and maximum power densities(MPD) of 289.9, 276.1 and $220.4mW/cm^2$ were measured at 800, 750 and $700^{\circ}C$, respectively. The proposed fabrication technique using decalcomania paper was shown to be feasible for the easy fabrication of segmented-in-series flattened tube SOFCs.

• 한국수소및신에너지학회논문집
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• 제23권5호
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• pp.468-475
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• 2012

A proper stacking force and assembly are important to the performance of fuel cell. Improper assembly pressure may lead to leakage of fuels and high interfacial contact resistance, excessive assembly pressure may result in damage to the gas diffusion layer and other components. The pressure distribution of gas diffusion layer is important to make interfacial contact resistance less for stack performance. To analyze the influence of design parameter factors for pressure distribution, and to optimize stack design, DOE (Design of Experiment) was used for polymer electrolyte membrane fuel cell stack pressure test. As commonly known, the higher clamping force improves the fuel cell stack performance. However, non-uniformity of stress distribution is also increased. It shows that optimization between clamping force and stress distribution is needed for well designed structure of fuel cell stack. In this study, stack design optimization method is suggested by using FEM (Finite Element Methode) and DOE for light-weighted fuel cell stack.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2000년도 추계학술대회 논문집
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• pp.84-89
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• 2000

Thermal simulation of typical stack-type and newly proposed planar-type micro-gas sensors were studied by FEM method. The thermal analyses for the proposed planar structure including temperatur distribution over the sensing layer and power consumption of the heater were carried using finite element method by computer simulation and well compared with those of typical stack-type micro-gas sensor. The thermal properties of the microsensor from thermal simulation were compared with those of a actual device to investigate the acceptability of the computer simulation.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2007년도 SMT/PCB 기술세미나
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• pp.37-47
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• 2007

Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

• International journal of advanced smart convergence
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• 제9권3호
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• pp.253-259
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• 2020

Most of today's large-scale cloud systems and enterprise data centers are distributing resources to improve scalability and resource utilization. NVMe-over-Fabric protocol allows submitting NVMe commands to a remote NVMe SSD through RDMA (Remote Direct Memory Access) network. It is attracting attention recently because it is possible to construct a disaggregation storage system with low latency through the protocol. However, the current I/O stack of NVMe-over-Fabric has an inefficient structure for maintaining compatibility with the traditional I/O stack. Therefore, in this paper, we propose a new mechanism to reduce I/O latency and CPU overhead by modifying I/O path of NVMe-over-Fabric to pass through legacy block layer. According to the performance evaluation results, the proposed mechanism is able to reduce the I/O latency and CPU overhead by up to 22% and 24% compared to the existing NVMe-over-Fabrics protocol, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• 융합보안논문지
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• 제5권4호
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• pp.19-25
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• 2005

스레드 트리란 LR 파싱표를 사용하여 파스 트리인 동시에 파스 스택을 표현 할 수 있는 자료구조이다. $Larchev\^{e}que$는 스택을 사용하여 스레드 트리들 구성하고 점진적 파싱을 한다. 본 논문에서는 재 파싱 노드와 파싱속도를 줄이기 위해 스택을 사용하지 않는 변화된 스레드 트리를 구성하는 알고리즘을 제안한다. 또한 노드의 재 파싱 과정을 없애기 위해 변화된 스레드 트리와 LR 파싱표를 사용하는 점진적 파싱 알고리즘을 제안한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.507-510
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• 2005

High voltage pulse power supply using Marx generator and solid-state switches is proposed in this study. The Marx generator is composed of 12 stages and each stage is made of IGBT stack, two diode stacks, and capacitor. To charge the capacitors of each stage in parallel, inductive charging method is used and this method results in high efficiency and high repetition rates. It can generate the pulse voltage with the following parameters: Voltage: up to 120kv Rising time: sub ${\mu}S$ Pulse width: up to $10{\mu}S$, Pulse repetition rate: 1000pps The proposed pulsed power generator uses IGBT stack with a simple driver and has modular design. So this system structure gives compactness and easiness to implement total system. Some experimental results are included to verify the system performances in this paper.