• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.448-448
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• 2010

Magnetic random access memory (MRAM) has made a prominent progress in memory performance and has brought a bright prospect for the next generation nonvolatile memory technologies due to its excellent advantages. Dry etching process of magnetic thin films is one of the important issues for the magnetic devices such as magnetic tunneling junctions (MTJs) based MRAM. CoFeB is a well-known soft ferromagnetic material, of particular interest for magnetic tunnel junctions (MTJs) and other devices based on tunneling magneto-resistance (TMR), such as spin-transfer-torque MRAM. One particular example is the CoFeB - MgO - CoFeB system, which has already been integrated in MRAM. In all of these applications, knowledge of control over the etching properties of CoFeB is crucial. Recently, transferring the pattern by using milling is a commonly used, although the redeposition of back-sputtered etch products on the sidewalls and the low etch rate of this method are main disadvantages. So the other method which has reported about much higher etch rates of >$50{\AA}/s$ for magnetic multi-layer structures using $Cl_2$/Ar plasmas is proposed. However, the chlorinated etch residues on the sidewalls of the etched features tend to severely corrode the magnetic material. Besides avoiding corrosion, during etching facets format the sidewalls of the mask due to physical sputtering of the mask material. Therefore, in this work, magnetic material such as CoFeB was etched in an ICP etching system using the gases which can be expected to form volatile metallo-organic compounds. As the gases, carbon monoxide (CO) and ammonia ($NH_3$) were used as etching gases to form carbonyl volatiles, and the etched features of CoFeB thin films under by Ta masking material were observed with electron microscopy to confirm etched resolution. And the etch conditions such as bias power, gas combination flow, process pressure, and source power were varied to find out and control the properties of magnetic layer during the process.

• 한국식품과학회지
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• 제49권3호
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• pp.252-257
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• 2017

식품의 다양한 가공특성별 조사처리 식품의 분석법 적용성을 검토하기 위하여 감마선과 전자선 조사처리 대두의 가공특성(건조, 분쇄) 및 원산지(국산, 중국산, 미국산)별 물리적 확인시험법을 이용한 판별 특성을 확인하였다. 광자극발광(PSL) 분석 결과 비조사시료는 266-395 count/min으로 $700^{\circ}C$ 이하의 값을 나타내어 음성(negative) 값으로 나타나 조사처리 되지 않은 시료로 확인되었다. 감마선과 전자선을 조사처리한 대두는 감마선의 경우 5,815-39,591 count/min, 전자선의 경우 5,791-60,055 count/min의 결과로 모두 5,000 count/min 이상인 양성(positive)값을 나타내어 대두는 가공특성, 선종, 선량에 관계없이 조사처리 판별이 가능한 것으로 나타났다. 열발광분석(TL)을 통한 조사처리 확인에서는 비조사 시료는 $300^{\circ}C$ 이상에서 자연방사선에 의한 발광곡선을 나타내었고 감마선과 전자선 조사처리 대두에서는 $150-250^{\circ}C$에서 조사처리에 의한 최대곡선을 나타내어 조사처리 판별이 가능하였다. 전자스핀공명 분석 결과는 건조대두의 껍질에서 조사 처리에 의한 cellulose radical이 확인되었으며 분쇄한 대두의 경우에는 비조사시료와 조사처리에 의한 뚜렷한 차이를 보이지 않아 조사처리 판별이 어려운 것으로 확인되었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.