• Proceedings of the Korean Radioactive Waste Society Conference
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• 2005.06a
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• pp.311-318
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• 2005

Transparency on the Total System Performance Assessment (TSPA) is the key issue to enhance the public acceptance for a permanent high level radioactive repository. To approve it, all performances on TSPA through Quality Assurance is necessary. The integrated Cyber R&D Platform is developed by KAERI using the T2R3 principles applicable for five major steps in R&D's. The proposed system is implemented in the web-based system so that all participants in TSPA are able to access the system. It is composed of FEAS (FEp to Assessment through Scenario development) showing systematic approach from the FEPs to Assessment methods flow chart, PAID (Performance Assessment Input Databases) showing PA(Performance Assessment) input data set in web based system and QA system receding those data. All information is integrated into Cyber R&D Platform so that every data in the system can be checked whenever necessary. For more user-friendly system, system upgrade included input data & documentation package is under development. Throughout the next phase R&D, Cyber R&D Platform will be connected with the assessment tool for TSPA so that it will be expected to search the whole information in one unified system.

• The Transactions of the Korea Information Processing Society
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• v.7 no.11S
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• pp.3651-3667
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• 2000

Recently, in the distributed multimedia environments based on internet, as radical growing technologies, the most of researchers focus on both streaming technology and distributed object thchnology, Specially, the studies which are tried to integrate the streaming services on the distributed object technology have been progressing. These technologies are applied to various stream service mamgements and protocols. However, the stream service management mexlels which are being proposed by the existing researches are insufficient for suporting the QoS of stream services. Besides, the existing models have the problems that cannot support the extensibility and the reusability, when the QoS-reiatedfunctions are being developed as a sub-module which is suited on the specific-purpose application services. For solving these problems, in this paper. we suggested a QoS Integrated platform which can extend and reuse using the distributed object technologies, and guarantee the QoS of the stream services. A structure of platform we suggested consists of three components such as User Control Module(UCM), QoS Management Module(QoSM) and Stream Object. Stream Object has Send/Receive operations for transmitting the RTP packets over TCP/IP. User Control ModuleI(UCM) controls Stream Objects via the COREA service objects. QoS Management Modulel(QoSM) has the functions which maintain the QoS of stream service between the UCMs in client and server. As QoS control methexlologies, procedures of resource monitoring, negotiation, and resource adaptation are executed via the interactions among these comiXments mentioned above. For constmcting this QoS integrated platform, we first implemented the modules mentioned above independently, and then, used IDL for defining interfaces among these mexlules so that can support platform independence, interoperability and portability base on COREA. This platform is constructed using OrbixWeb 3.1c following CORBA specification on Solaris 2.5/2.7, Java language, Java, Java Media Framework API 2.0, Mini-SQL1.0.16 and multimedia equipments. As results for verifying this platform functionally, we showed executing results of each module we mentioned above, and a numerical data obtained from QoS control procedures on client and server's GUI, while stream service is executing on our platform.

• Journal of IKEEE
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• v.19 no.2
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• pp.276-281
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• 2015

Engineers increasingly rely on computers and their computer programming skills for their works. As a result, most engineering curricula have introduced a computer programming courses. However, students consider the subject to be unrelated to their core interests and often feel uncomfortable when learning to program for the first time. To overcome these difficulties, several studies have proposed the use of physical computing paradigm. This paradigm takes the computational concepts out of the PC screen and into the real world so that the student can interact with them. This paper proposes Arduino platform as a tool for attracting interest of the programming and reports the results of questionnaire survey analysis.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.177-179
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• 2009

It is increased that need of broadband multimedia service to make useful environment for user and to support the operation of railway system. So study of integrated data transmission in a subway and railway is activated. The research deals with pass loss characteristics of 18GHz microwave that is assigned frequency of integrated data transmission in a subway and railway. It is used sample integrated transmission system in subway and railway of KRRI(korea railroad research Institute) at the tunnel and road. Specification of test sample system is blow. It use OFDM modulation, Wireless frequency is 18GHz and 19GHz, Maximum output power is 20dBm, Receive sensitivity is -90dBm. The pass loss exponent and standard variation of road and tunnel is analyzed.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.699-708
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• 2006

Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

• The KIPS Transactions:PartC
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• v.10C no.5
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• pp.585-594
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• 2003

Java card is one of promising smart card platform with java technology. Java card defines necessary packages and classes for Embedded device that have small memory such as smart card Jana card is compatible with EMV that is Industry specification standard and ISO-7816 that is international standard. However, Java card is not offers user authentication protocol. In this paper, We design and implement an user authentication protocol applicable wireless devices based on Java Card using standard 3GPP Specification (SMS), Java Card Specification (APDU), Cryptography and so on. Our Java Card user authentication techniques can possibly be applied to the area of M-Commerce, Wireless Security, E-Payment System, Mobile Internet, Global Position Service, Ubiquitous Computing and so on.

• The KIPS Transactions:PartC
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• v.13C no.5 s.108
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• pp.583-594
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• 2006

The reliability concept of wireless sensor network is essential to get exactly actual data from the ubiquitous environment. A rollback technique for the self-healing helps to increase it. However, a fault can occur in wireless sensor network when to use a previous rollback technique because it is designed just for the local system. So, checkpoint protocols are suggested in order to use a rollback technique in the network without the fault. However, there is trade-off among performance overhead, power consumption, and memory overhead for each of protocols. Hence, we suggest a novel global checkpoint protocol, so called address log based protocol(ALBP), based on an asynchronous protocol. It is a platform based protocol to reduce power consumption, performance overhead, and memory overhead which are the most of consideration in wireless sensor network.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.1
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• pp.191-198
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• 2020

In this study, we proposed a real-time ECG analytical method for predicting stress and dangerous heart condition using the ECG signal in playing AR/VR device. A real-time diagnosis is used as R-R interval based HRV(:Heart rate variability), BPM(:Beats Per Minitue) and autonomic nervous research with through mapping method of two-dimensional planes. The ECG data were analyzed every 5 minutes and derived from autonomic nervous system diagnosis.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.570-572
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• 2006

This paper discusses the method of moving object detection for biped robot walking. Most researches on vision based object detection have mostly focused on fixed camera based algorithm itself. However, developing vision systems for biped walking robot is an important and urgent issue since hired walking robots are ultimately developed not only for researches but to be utilized in real life. In the research, method for moving object detection has been developed for task assignment and execution of biped robot as well as for human robot interaction (HRI) system. But these methods are not suitable to biped walking robot. So, we suggest the advanced method which is suitable to biped walking robot platform. For carrying out certain tasks, an object detecting system using modified optical flow algorithm by wireless vision camera is implemented in a biped walking robot.

• ETRI Journal
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• v.28 no.4
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).