• 한국광학회지
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• 제23권6호
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• pp.269-273
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• 2012

배광 분포 제어가 용이한 높이 분할방식 반사컵 설계를 수행함에 있어서, 배광 설계시 배광 분포의 설계오차를 줄이기 위하여, LED 칩 표면상의 광량 분포 변화에 따른 반사컵의 배광 특성 변화 경향성을 파악하여 최적 설계에 적용하였다. LED 패키지의 반사컵을 높이에 따라 2단 분할하여 최적 설계한 결과, 교차형과 비교차형의 조합 설계를 통해서 최대 광도와 균일도를 조절하거나 암흑 영역을 없애는 등 다양한 기능성 설계가 가능했다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.193-196
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• 2000

In this paper, the performance of DS-CDMA system with smart antenna is analyzed for different bandwidths (1.25MHz, 5MHz) and different channel environments (rural, urban). For the analysis of smart antenna system, the vector channel model having the spatio-temporal correlation is needed. Hence, the channel is modeled as a time-variant linear filter in time, and each multipath is assumed as a reflective wave from only one direction (only one cluster) in space. A simulation is carried out by dividing several multipaths within one chip into each one and searching the strongest signal. DS-CDMA system with smart antenna using wider bandwidth present better performance than that using narrow bandwidth. It is shown that the smart antenna is more effective in urban area when using 2D-RAKE receiver.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 제13회 신호처리 합동 학술대회 논문집
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• pp.79-82
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• 2000

In this paper, the performance of 05-CDMA system with smart antenna is analyzed for different bandwidths (1.25MHz, 5MHz) and different channel environments (rural, urban). For the analysis of smart antenna system, the vector channel having the spatio-temporal correlation is modeled as a time-variant linear filter in time, and each multipath is assumed as a reflective wave from only one direction (only one cluster) in space. Several multipaths within one chip are distinguished into each one and the strongest signal is selected. DS-CDMA system with smart antenna using wider bandwidth present better performance than that using narrow bandwidth. It is shown that the smart antenna is more effective in urban area when using 2D-RAKE receiver.

• 제어로봇시스템학회논문지
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• 제18권11호
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• pp.1018-1026
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• 2012

This paper presents a developing method of smart fingerprint recognition system. First, we design a hardware configuration circuit using a 32bit Risc CPU, a fingerprint sensor, a LCD, and a WiFi communication chip to realize the smart fingerprint recognition systems. It is necessary to develop a JNI (Java Native Interface) library and a device drive program of fingerprint sense to develop application program of fingerprint recognition system with Android platform. Thus second, we develop a device drive and a JNI program. And we also develop an application program of fingerprint recognition systems using developed JNI library. Finally test results are presented to illustrate the performance of the developed smart fingerprint recognition system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1689-1692
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• 2002

In this paper, the performance of DS-CDMA system with smart antenna is analyzed for different bandwidths (1.25MHz, 5MHz) and different channel environments (rural, urban). For the analysis of smart antenna system, the vector channel having the spatio-temporal correlation is modeled as a time- variant linear filter in time, and each multipath is assumed as a reflective wave from only one direction (only one cluster) in space. Several multipaths within one chip are distinguished into each one and the strongest signal is selected. DS-CDMA system with smart antenna using wider bandwidth present better performance than that using narrow bandwidth. It is shown that the smart antenna is more effective in urban area when using 2D-RAKE receiver.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2011년 춘계학술대회논문집
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• 한국재료학회지
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• 제29권2호
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• pp.106-115
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• 2019

Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.349-352
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• 2002

In this Paper, we introduced 32 bit SOC implementation for multi-application Smart Card and described the methodology for reducing power consumption. It consists of ARMTTDMI micro-processor, 192 KBytes EEPROM, 16 KB SRAM, crypto processors and card reader interface based on AMBA bus system. We used Synopsys Power Compiler to estimate and optimize power consumption. Experimental results show that we can reduce Power consumption up to 62 % without increasing the chip area.

• Smart Structures and Systems
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• 제12권1호
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• pp.23-39
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• 2013

In this article, a smart multifunctional optical system-on-a-chip (SOC) sensor platform is presented and its application for fiber Bragg grating (FBG) sensor interrogation in optical sensor networks is investigated. The smart SOC sensor platform consists of a superluminescent diode as a broadband source, a tunable microelectromechanical system (MEMS) based Fabry-P$\acute{e}$rot filter, photodetectors, and an integrated microcontroller for data acquisition, processing, and communication. Integrated with a wireless sensor network (WSN) module in a compact package, a smart optical sensor node is developed. The smart multifunctional sensor platform has the capability of interrogating different types of optical fiber sensors, including Fabry-P$\acute{e}$rot sensors and Bragg grating sensors. As a case study, the smart optical sensor platform is demonstrated to interrogate multiplexed FBG strain sensors. A time domain signal processing method is used to obtain the Bragg wavelength shift of two FBG strain sensors through sweeping the MEMS tunable Fabry-P$\acute{e}$rot filter. A tuning range of 46 nm and a tuning speed of 10 Hz are achieved. The smart optical sensor platform will open doors to many applications that require high performance optical WSNs.

• International journal of advanced smart convergence
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• 제11권2호
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• pp.53-58
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• 2022

In this paper, w-band frequency synthesizer was developed for frequency-modulated continuous wave (FMCW) radar sensors. To achieve a small size and high performance, We designed and manufactured w-band MMIC chips such as up-converter one-chip, multiplier, DA (Drive Amplifier) MMIC(Monolithic Microwave Integrated Circuit), etc. And interposer technology was applied between the W-band multiplier and the DA MMIC chip. As a result, the measured phase noise was -106.10 dBc@1MHz offset, and the frequency switching time of the frequency synthesizer was less than 0.1 usec. Compared with the w-band frequency synthesizer using purchased chips, the developed frequency synthesizer showed better performance.