• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.430-435
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• 2018

In this paper, an improved decoding scheme for low-complexity parity-check(LCPC) code with small code length is proposed. The LCPC code is less complex than the turbo code or low density parity check(LDPC) code and requires less memory, making it suitable for communication between internet-of-things(IoT) devices. The IoT devices are required to have low complexity due to limited energy and have a low end-to-end delay time. In addition, since the packet length to be transmitted is small and the signal processing capability of the IoT terminal is small, the LCPC coding system should be as simple as possible. The LCPC code can correct all single errors and correct some of the two errors. In this paper, the proposed decoding scheme improves the bit error rate(BER) performance without increasing the complexity by correcting both errors using the soft value of the modulator output stage. As a result of the simulation using the proposed decoding scheme, the code gain of about 1.1 [dB] was obtained at the bit error rate of $10^{-5}$ compared with the existing decoding method.

• Journal of Communications and Networks
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• v.16 no.5
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• pp.479-484
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• 2014

In this paper, we consider the construction of cyclic and quasi-cyclic structured q-ary low-density parity-check (LDPC) codes over a designated small field. The construction is performed with a pre-defined sliding-window, which actually executes the regular mapping from original field to the targeted field under certain parameters. Compared to the original codes, the new constructed codes can provide better flexibility in choice of code rate, code length and size of field. The constructed codes over small fields with code length from tenths to hundreds perform well with q-ary sum-product decoding algorithm (QSPA) over the additive white Gaussian noise channel and are comparable to the improved spherepacking bound. These codes may found applications in wireless sensor networks (WSN), where the delay and energy are extremely constrained.

• Journal of The Korean Astronomical Society
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• v.27 no.1
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• pp.13-29
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• 1994

We have constructed a 3-dim hydrodynamics code called BTSPH. The fluid dynamics part of the code is based on the smoothed particle hydrodynamics (SPH), and for its Poisson solver the binary tree (BT) scheme is employed. We let the smoothing length in the SPH algorithm vary with space and time, so that resolution of the calculation is considerably enhanced over the version of SPH with fixed smoothing length. The binary tree scheme calculates the gravitational force at a point by collecting the monopole forces from neighboring particles and the multipole forces from aggregates of distant particles. The BTSPH is free from geometric constraints, does not rely on grids, and needs arrays of moderate size. With the code we have run the following set of test calculations: one-dim shock tube, adiabatic collapse of an isothermal cloud, small oscillation of an equilibrium polytrope of index 3/2, and tidal encounter of the polytrope and a point mass perturber. Results of the tests confirmed the code performance.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.215-218
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• 1998

This paper proposes a blind multi-user detector using Code-Constrained Minimum Variance (CCMV) method which directly detects the DS-CDMA signals in a multipath fading channel without estimating the channels. This algorithm reduces the complexity of computation by making a small size data matrix with the order of the channel length. Advantageously it requires to know the spreading code and the time delay of only the desired user.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.1
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• pp.27-33
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• 1975

The required minimum size of character diode matrix of Korean letters is estimated from the topological complexity of letter structure. The OR aombination of three letter boards (diode matrice) gives all possible Hangout whole letters in proper traditional combined form with minimum required discernibility. Two forms of first consonants (centre located ones for horizontal vowels and leftward displaced ones for vertical and composed vowels) are switched by only 1 bit of the vowel code. The vowel pattern length is modified by again the last four bits of the code. A new 15bit sized inner code is proposed which permits considerably small sized decoding mechanism.

• Journal of Communications and Networks
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• v.14 no.2
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• pp.195-198
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• 2012

An efficient sliding window algorithm employing an adaptive-length guard window for turbo decoders is proposed. The proposed algorithm results in significant complexity reductions, especially for small sliding window lengths where the additional computational complexity required for the guard window is critical.

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• Journal of the Earthquake Engineering Society of Korea
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• v.18 no.4
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• pp.171-180
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• 2014

Since the execution of structural design by professional structural engineers is not mandatory for small-size buildings in Korea, structural design is conducted by architects or contractors resulting in concern about the seismic safety of the buildings. Therefore, the Korean Structural Engineers Association proposed dedicated structural design criteria in 2012. The criteria were developed based on a deterministic approach in which the structural members are designed only with information of story and span length of the buildings and without structural analyses. However, due to the short time devoted to their development, these criteria miss satisfactory basis and do not deal with structural walls popularly used in Korea. Accordingly, the Ministry of Land, Infrastructure and Transport launched a research on the 'development of structural performance enhancement technologies for small-size buildings against earthquakes and climate changes'.. As part of this research, this paper intends to establish direction for the preparation of deterministic structural design guidelines for seismic safety of domestic small-size reinforced concrete buildings. To that goal, a typical plan of these buildings is selected considering frames only and frames plus walls, and then design is conducted by changing the number of stories and span length. Next, the seismic performance is analyzed by nonlinear static pushover analysis. The results show that the structural design guidelines should be developed by classifying frames only and frames plus walls. The size and reinforcement of structural elements should be provided in the middle level of the current Korean Building Code and criteria for small buildings by considering story and span length for buildings with frames only, and determined by considering the shape and location of walls and the story and span length as well for buildings with frames plus walls. It is recommended that the design of walls should be conducted by reducing the amount of walls along with symmetrically located walls.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• Journal of IKEEE
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• v.20 no.4
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• pp.449-453
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• 2016

Failures would occur because of the hostile nature environment in Wireless Sensor Networks (WSNs) which is deployed randomly. Therefore, considering faults in WSNs is essential when we design WSN. This paper classified fault model in the sensor node. Especially, this paper proposed new error correcting code scheme and fault recovery algorithm in the CH(Cluster Head) node. For the range of the small size information (<16), the parity size of the proposed code scheme has the same parity length compared with the Hamming code, and it has a benefit to generate code word very simple way. This is very essential to maintain reliability in WSN with increase power efficiency.