• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.697-699
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• 2017

본 논문에서는 D 플립플롭과 보조 전하펌프를 사용하여 작은 크기의 위상고정루프를 제안하였다. 단일 커패시터를 사용하여 크기가 작기 때문에 위상고정루프의 집적화가 가능하다. 제안된 위상고정루프는 HSPICE로 시뮬레이션 하였으며, 1.8V $0.18{\mu}m$ CMOS 공정을 사용하였다.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.207-212
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• 2013

A new CMOS voltage-bias differential LC voltage-controlled oscillator (LC-VCO) with active source degeneration is proposed. The proposed degeneration technique preserves the quality factor of the LC-tank which leads to improvement in phase noise of VCO oscillators. The proposed VCO shows the high figure of merit (FOM) with large tuning range, low power, and small chip size compared to those of conventional voltage-bias differential LC-VCO. The proposed VCO implemented in 0.18-${\mu}m$ CMOS shows the phase noise of -118 dBc/Hz at 1 MHz offset oscillating at 5.03 GHz, tuning range of 12%, occupies 0.15 $mm^2$ of chip area while dissipating 1.44 mW from 0.8 V supply.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.1042-1047
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• 2001

A mechanistic model is developed to predict the thrust force and cutting torque of drilling process including wear. A mechanistic oblique cutting force model is used to develop the drilling force model. The cutting lips are divided into small elements and elemental forces are calculated by multiplying the specific cutting pressure with the elemental chip area. The specific cutting pressure is a function of chip thickness, cutting velocity, rake angle and wear. The total forces are then computed by summing the elemental forces. Measured cutting forces are in good agreement with the simulated cutting forces.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.376-379
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• 1999

The wavelet transform chip is implemented with Daubechies' 4 tap filter. It works at 20MHz in Field Programmable Gate array (FPGA) implementation of Quadrature Mirror Filter(QMF) Lattice Structure. In this paper, the structure contains taro-channel quadrature mirror filter, data format converter(DFC), delay control unit(DCU), and three 20$\times$8 bits real multiplier. The structures for the DFC and DCU need to he regular and scalable, require minimum number of regular, and thereby lead to an efficient and scalable architecture for the Discrete Wavelet Transform(DWT). These results present the possibility that it can be used in Digital Signal Processing(DSP) application faster than Fourier transform at small area with lour cost.

• 대한설비공학회:학술대회논문집
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• 대한설비공학회 2007년도 동계학술발표대회 논문집
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• pp.640-645
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• 2007

An experimental apparatus to show the hot spot cooling of an IC chip using a thermoelectric cooler is developed. The spot heating in very small area is achieved by the applying CO$_2$ laser source and temperatures are measured using miniature thermocouples. The active effects of thermoelectric cooler on the hot spot cooling system such as rapid heat spreading in the chip and lowering the peak temperature around the hot spot region are investigated. The experimental results are simulated numerically using the TAS program, which the performance characteristics such as Seebeck coefficient, electrical resistance and thermal conductivity of the thermoelectric cooler are searched by trial and error. Good agreements are obtained between numerical and experimental results if the appropriate performance data of the thermoelectric cooler are given.

• 전자공학회논문지A
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• 제32A권10호
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• 대한전자공학회논문지SD
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• 제46권4호
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• pp.1-9
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• 2009

본 논문에서는 디스플레이 시스템을 위한 소면적 12-bit 300MSPS의 D/A 변화기(DAC)를 제안한다. 최근 SoC(System-On-Chip) 경향에 맞는 소면적 DAC를 구현하기 위한 전체적인 구조는 6-MSB(Most Significant Bit) + 6-LSB(Least Significant Bit)의 full matrix 구조로 설계 하였다. 고해상도 동작에 요구되는 output impedance을 만족하는 monitoring bias 구조, 고속 동작 및 소면적 디지털 회로 구성을 위하여 logic과 latch 및 deglitching 역할을 동시에 할 수 있는 self-clocked switching logic을 각각 제안하였다. 설계된 DAC는 Samsung $0.13{\mu}m$ thick gate 1-poly 6-metal N-well CMOS 공정으로 제작되었다. 제작된 DAC의 측정결과 INL (Integrated Non Linearity) / DNL (Differential Non Linearity)은 ${\pm}3LSB$ / ${\pm}1LSB$ 이하로 나타났으며, 300MHz 샘플링 속도와 15MHz의 출력신호에서 SFDR은 약 70dB로 측정되었다. DAC의 유효면적은 $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$)로 기존의 DAC에 비하여 최대 40% 감소된 초소면적으로 구현되었으며, 최대 전력 소모는 100mW로 측정되었다.

• Journal of the Korean Data and Information Science Society
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• 제20권1호
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• pp.125-137
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• 2009

스마트카드는 작은 크기의 마이크로 컴퓨터칩을 내장하고 있다. 이 칩은 프로세서, RAM, ROM, 클럭, 버스 그리고 암호전용 코프로세서 등을 포함하고 있다. 따라서 이 칩은 RFID 태그와 비교해서 가격이 비싸고, 복잡하지만 안전한 칩이다. 스마트카드의 주요 응용분야는 전자뱅킹이나 안전한 통신 관련 분야이다. 자바카드는 개방형 플랫폼 중 가장 널리 사용되는데 그 이유는 자바카드의 보안성, 플랫폼 독립성, 그리고 빠른 개발 싸이클 때문이다. 하지만 자바카드는 실행속도가 느리기 때문에 자바 카드의 성능개선은 중요한 연구 분야가 되어왔다. 본 논문에서는 효과적인 트랜잭션버퍼 관리 방법을 제안하여 자바카드의 성능을 개선시켰으며 실험을 통하여 그 성능을 입증하였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.404-407
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• 2011

본 논문은 전류모드에서 동작하는 PWM/PFM DC-DC Boost 변환기의 설계를 하였다. 부하전류가 클 때는 PWM으로 동작하고, 부하 전류가 작을 때는 PFM으로 동작함으로써 높은 효율을 유지할 수 있게 설계하였다. DC-DC Boost 변환기는 $0.35{\mu}m$ 공정으로 설계되었으며, 500KHz의 주파수에 동작하고, 최대 효율은 92.1%이다. 그리고 부하 전류가 최대 600mA까지 구동 할 수 있다. 전체 칩의 크기는 패드를 포함하여 $1300{\mu}m{\times}1070{\mu}m$이다. 따라서 작은 칩 면적으로 넓은 부하전류를 구동할 수 있는 DC-DC Boost 변환기를 설계하였다.