• Title/Summary/Keyword: Sj memory

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A Study on High Speed LDPC Decoder Algorithm Based on DVB-S2 Standard (멀티미디어 기반 해상통신을 위한 DVB-S2 기반 고속 LDPC 복호를 위한 알고리즘에 관한 연구)

  • Jung, Ji Won;Kwon, Hae Chan;Kim, Yeong Ju;Park, Sang Hyuk;Lee, Seong Ro
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.3
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    • pp.311-317
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    • 2013
  • In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.