• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.511-517
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• 2006

The key issues in high power, high energy applications such as electromagnetic launchers include safety, reliability, flexibility, efficiency, compactness, and cost. To explore some of the issues, a control scheme for a large current wave-forming was designed, built and experimentally verified using a 2.4MJ pulse power system (PPS). The PPS was made up of eight capacitors bank unit, each containing six capacitors connected in parallel. Therefore there were 48 capacitors in total, with ratings of 22kV and 50kJ each. Each unit is charged through a charging switch that is operated by air pressure. For discharging each unit has a triggered vacuum switch (TVS) with ratings of 200kA and 250kV. Hence, flexibility of a large current wave-forming can be obtained by controlling the charging voltage and the discharging times. The whole control system includes a personal computer(PC), RS232 and RS485 pseudo converter, electric/optical signal converters and eight 80C196KC micro-controller based capacitor-bank module(CBM) controllers. Hence, the PC based controller can set the capacitor charging voltages and the TVS trigger timings of each CBM controller for the current wave-forming. It also monitors and records the system status data. We illustrated that our control scheme was able to generate the large current pulse flexibly and safely by experiments. The our control scheme minimize the use of optical cables without reducing EMI noise immunity and reliability, this is resulting in cost reduction. Also, the reliability was increased by isolating ground doubly, it reduced drastically the interference of the large voltage pulse induced by the large current pulse. This paper contains the complete control scheme and details of each subsystem unit.