• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.179-181
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• 1998

In this paper, one chip PWM pattern generator which eliminates time delay of computations and improves utilization factor of voltage is proposed. Both amplitude of sinusoidal signal and triangular signal are directly controlled. Thus, time delay of computations can be eliminated, and it is possible to track accurately instantaneous current for a sudden change of load with microprocessor 80C196KC. In addition, setting dead-time is also possible for wide range. From experimental work with inverter system for driving induction motor, the validity of proposed one chip PWM pattern generator is verified.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.268-270
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• 1995

This paper proposes a novel PWM technique for a three phase current fad type converters. A minor loop compensation method is introduced to compensate leading current and to minimize input line current (Iu) distortion resulting from the resonance between AC filter capacitor and source inductance of power system. This PWM converter has excellent characterics as next. The control system is simply designed, and the operation with unity power factor can be easily obtained by automatic compensating the leading current of the filter circuit. Also. the three phase sinusoidal input current can be obtained.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.3
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• pp.27-33
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• 1993

This paper presents the &tal controller for driving high frequency voltage fed PWM inverter that carrier frequency is over 2OkHz.We analyzed the conventional PWM to select a proper PWM pattern. as the result, obtained PWM pattern of the controller in which asynchronus staircase sinusoidal waveform is used as reference signal, and variable carrier ratio method was used for PWM control. The PWM controller is designed by fully digital method. Especially, Thk proposed controller is consisted of 8 bit one-chip microprocessor and digital logic. the former is for arithmetic and data processing, and the latter is for PWM pattern synthesis. Therefore, The responsibility and controllability is improved. Also, Data processing capability is improved using proper program to output modulation index with 9 bits. Circuits configuration of digital controller are made up of one chip 8051 and EPLD, and its controllability is tested by operating voltage fed inverter. Harmonics and current waveform is evaluated and analyzed for the voltage fed inverter system.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.8
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• pp.448-454
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• 1999

This paper describes a new dc-ac inverter system which for achieving sinusoidal ac waveform makes use of parallel loaded high frequency resonant inverter consisting of full bridge. Each one of the pair of switches in the inverter is driven to synchronous output frequency and the other is driven to PWM signal with resonant frequency proportional to magnitude of sine wave. A forced discontinuous conduction mode is used to realize the quasi-sinusoidal pulse in each switching period. Therefore the inverter generates sinusoidal modulated output voltage including carrier frequency that is resonant frequency. Carrier frequency components of modulated output voltage is filtered by low pass filter. Since current through switches is always zero at its turn-on in the proposed inverter, low stress and low switching loss is achieved. Operating characteristics of the proposed system is analyzed in per unit system using computer simulation. The output voltage of if includes low harmonics and it is almost close to sine wave. Also, the theoretical analysis is proved through the experimental test.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.4
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• pp.322-331
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• 2002

In this paper, a single-phase to three-phase PWM converter topology using a single-phase half-bridge PWM rectifier and a 2-leg inverter for low cost three-phase induction motor drives is proposed. In addition, the source voltage sensor is eliminated with a state observer which controls the deviation between the model current and the system current to be zero. The converter topology is of lower cost than the conventional one, which gives sinusoidal input current, unity power factor, dc output voltage control, bidirectional power flow and VVVF output voltage. The experimental results for V/F control of 3Hp induction motor drives have been shown.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.63-68
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• 2002

In a utility interactive photovoltaic generation system, a PWM inverter is used for the connection between the photovoltaic arrays and the utility. The do current becomes pulsated when the conventional inverter system operates in the continuous current mode and dc current pulsation causes the distortion of the ac current waveform. To reduce pulsation of dc input current, This paper presents a Buck-Boost PWM power inverter and its application for residential photovoltaic system. The PWM power inverter is realized by combining two sets of a high frequency Buck-Boost chopper and by making it operate in the discontinuous conduction mode. In this paper, we show the Buck-Boost PWM power inverter circuit, its equivalent circuit and basic differential equations and the power flow characteristics are clarified when the proposed Inverter is interconnected with the utility lines. In conclusion, the proposed inverter system provides a sinusoidal ac current for domestic loads and the utility line with unity power factor

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.2
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• pp.36-40
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• 1993

In order to improve complicated construction and complex control which are disadvantage of optimal PWM technique aimed at harmonic elimination method, this paper presented MRA(Model Reference Adaptive) PWM technique that gatmg signal of inverter is generated by comparing the reference signal with the induced feedback signal at the reference model of load. Design of controller is composed of microprocessor and analog circuit. MRA PWM technique used in the paper is able to compensate the degradation of voltage efficiency to be generated by the ratio of the output voltage to the DC supply voltage being low for using conventional sinusoidal PWM technique. When the trapezoidal signal is employed as the reference signal. the low order harmonics of line current can be reduced and the switching pattern is made by on-line computation using comparatively simple numerical analysis.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.4
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• pp.502-509
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• 2013

It presents an efficient switching pattern, which expects a reduction of switching losses in a cascaded H-bridge PWM multilevel inverter. By the proposed switching scheme, the lower H-bridge module operates at low frequency of 60[Hz] because it assigns to transfer most load power. The upper H-bridge module operates at high frequency of PWM switching to improve THD of output voltage. The proposed switching pattern applies to cascaded H-bridge multilevel inverter with PD, APOD, bipolar, and unipolar switching methods. By computer-aided simulations, we verify the validity of the proposed switching scheme. Finally, we prove that the proposed PD and APOD switching patterns are better than those of the conventional one in efficiency.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.9
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• pp.618-625
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• 2000

Recently PWM inverters are widely utilized for many industrial applications e.g. high performance motor drive and PWM techniques are newly developed for an accurate output voltage. Among them space voltage vector PWM(SVPWM) inverter has high voltage ratio and low harmonics compared to the conventional sinusoidal PWM inverter. However output voltage of PWM inverter is distorted and has error duet o the conducting voltage drop of switching devices and the dead time that is inevitable to prevent the shoot-through phenomenon. This paper investigates 3-phase SVPWM inverter which has a new compensation method against dead time and voltage drop. Proposed algorithm calculates gate pulse periods which directly compensates the dead time and nonlinear voltage drop without modification of reference voltages. Direct compensation of gate pulse periods produces exact output voltage and does not need additional circuits. The propose algorithm is verified through the simulation and experiments.

• Journal of Electrical Engineering and Technology
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• v.8 no.2
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• pp.295-303
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• 2013

This paper reports an investigation of pulse width modulation (PWM) techniques for two-phase brushless DC (BLDC) motors fed by a two-phase eight-switch inverter in a fan application. The three-phase BLDC motor is widely applied in industry; however, a lower-cost two-phase BLDC motor and drive circuit has been greatly in demand in recent years. In this paper, we introduce a mathematical model of the two-phase BLDC motor with sinusoidal back electromotive forces (EMFs) based on traditional three-phase BLDC motors. To simplify the drive algorithm and speed up its application, we analyze the principle of block commutation for a two-phase BLDC motor drive in the 180-electrical-degree conduction mode, and we further propose five PWM schemes to improve the commutation performance of the two-phase BLDC drive. The effectiveness of the proposed PWM methods is verified through experiments.