• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.82.3-82
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• 2001

This work presents a design technique for the implementation of the liquid level control system by based on the use of a single-chip microcontroller. The proposed model system offers the following attractive features : (1) application of the pressure transducer for sensing the height of liquid in tank (2) using the obtained liquid level for defining on-off condition of the water pump (3) the liquid values were controlled by using stepping motors for controlling of 57 points (4) can set up by using manual control or automatic control (5) can monitor and display the process status either on microcontroller-based control board or on the computer via RS232 serial-port. Experimental results have been employed to show the effectiveness ...

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 1996.06c
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• pp.834-841
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• 1996

Egg production in Korea is becoming automated with a large scale farm. Although many operations in egg production have been and cracks are regraded as a critical problem. A computer vision system was built to generate images of a single , stationary egg. This system includes a CCD camera, a frame grabber board, a personal computer (IBM PC AT 486) and an incandescent back lighting system. Image processing algorithms were developed to inspect egg shell and to sort eggs. Those values of both gray level and area of dark spots in the egg image were used as criteria to detect holes in egg and those values of both area and roundness of dark spots in the egg and those values of both area and roundness of dark spots in the egg image were used to detect cracks in egg. Fro a sample of 300 eggs. this system was able to correctly analyze an egg for the presence of a defect 97.5% of the time. The weights of eggs were found to be linear to both the projected area and the perimeter of eggs v ewed from above. Those two values were used as criteria to sort eggs. Accuracy in grading was found to be 96.7% as compared with results from weight by electronic scale.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of Positioning, Navigation, and Timing
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• v.6 no.4
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• pp.195-203
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• 2017

A 2U cube satellite called SNUGLITE has been developed by GNSS Research Laboratory in Seoul National University. Its main mission is to perform actual operation by mounting dual-frequency global positioning system (GPS) receivers. Its scientific mission aims to observe space environments and collect data. It is essential for a cube satellite to control an Earth-oriented attitude for reliable and successful data transmission and reception. To this end, an attitude estimation and control algorithm, Attitude Determination and Control System (ADCS), has been implemented in the on-board computer (OBC) processor in real time. In this paper, the Extended Kalman Filter (EKF) was employed as the attitude estimation algorithm. For the attitude control technique, the Linear Quadratic Gaussian (LQG) was utilized. The algorithm was verified through the processor in the loop simulation (PILS) procedure. To validate the ADCS algorithm in the ground, the experimental verification via a single axis Hardware-in-the-loop simulation (HILS) was used due to the simplicity and cost effectiveness, rather than using the 3-axis HILS verification (Schwartz et al. 2003) with complex air-bearing mechanism design and high cost.

• The Journal of the Acoustical Society of Korea
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• v.36 no.1
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• pp.57-63
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• 2017

This paper presents an active acoustic-reflection control algorithm based on a single sensor. The proposed algorithm operates in a system comprising a single sensor located nearby the reflective surface and a control transducer mounted on the reflective surface. First, the incident and reflected acoustic signals are separated from the sensor signal, and a control signal is generated using the separated signals. For the signal separation, the proposed algorithm requires the response of the reflection path which is estimated from the acoustic response between an external sound source and the sensor. Finally, the control filter is adjusted using the FxLMS (Filtered-x Least Mean Square) algorithm. To verify the effectiveness of the proposed algorithm, it was implemented in real time using a DSP (Digital Signal Processing) board, and the experimental results obtained in one-dimensional air-acoustic environment show that the reflections of the 1 kHz burst can be reduced by 11.6 dB.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1131-1135
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• 2010

This paper presents a method to capture the posture of the human lower-limbs on the 3D space by using a single camera and a planar mirror. The system estimates the pose of the camera facing the mirror by using four coplanar IR markers attached on the planar mirror. After that, the training space is set up based on the relationship between the mirror and the camera. When a patient steps on the weight board, the system obtains relative position between patients' feet. The markers are attached on the sides of both legs, so that some markers are invisible from the camera due to the self-occlusion. The reflections of the markers on the mirror can partially resolve the above problem with a single camera system. The 3D positions of the markers are estimated by using the geometric information of the camera on the training space. Finally the system estimates and visualizes the posture and motion of the both legs based on the 3D marker positions.

• Journal of Biosystems Engineering
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• v.7 no.2
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• pp.18-29
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• 1983

A low cost and versatile data acquisition system for the field and laboratory use was developed by using a single board microcomputer. Data acquisition system based on a Z80 microprocessor was built, tested and modified to obtain the present functional system. The microcomputer developed consists of 6 kB ROM, 5 kB RAM, 6-seven segment LED display, 16-Hex. key and 8 command key board. And it interfaces with an 8 channel, 12 bits A/D converter, a microprinter, EPROM programmer for 2716, and RS232C interface to transfer data between the system and HP3000 mini-computer manufactured by Hewlett Packard Co., A software package was also developed, tested, and modified for the system. This package included drivers for the AID converter, LED display, key board, microprinter, EPROM programmer, and RS232c interface. All of these programs were written in 280 assembler language and converted to machine codes using a cross assembler by HP3000 computer to the system during modifying stage by data transferring unit of this system, then the machine language wrote to the EPROM by this EPROM programmer. The results are summarized as follows: 1. Measuring program developed was able to control the measuring intervals, No. of channels used, and No. of data, where the maximum measuring speed was 58.8 microsec. 2. Calibration of the system was performed with triangle wave generated by a function generator. The results of calibration agreed well to the test results. 3. The measured data was able to be written into EPROM, then the EPROM data was compared with original data. It took only 75 sec. for the developed program to write the data of 2 kB the EPROM. 4. For the slow speed measurements, microprinter instead of EPROM programmer proved to be useful. It took about 15 min. for microprinter to write the data of 2 kB. 5. Modified data transferring unit was very effective in communicating between the system and HP3000 computer. The required time for data transferring was only 1~2 min. 6. By using DC/DC converting devices such as 78-series, 79-series. and TL497 IC, this system was modified to convert the only one input power sources to the various powers. The available power sources of the system was DC 7~25 V and 1.8 A.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.359-364
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• 2006

Interference can seriously degrade the performance of GPS receiver because GPS signal has extremely low power at earth surface. This paper presents a Narrowband Interference Excision Filter (NIEF) in frequency domain that removes narrowband interferences with small signal loss. A NIEF transforms the received GPS signals with interferences into the frequency domain with FFT and then compute statistics such as mean and standard deviation to determine an excision threshold. All spectrums exceeding the threshold are removed and the remaining spectrums are restored by IFFT. A NIEF effectively can remove various and strong interferences with a simple structure. However, the signal power loss is unavoidable during FFT and IFFT. Besides the hamming window and overlap technique, a threshold-whitening technique and an adaptive detection threshold are adopted to effectively reduce the signal power loss. The performance of implemented NIEF is evaluated using real signals obtained by 12 bit GPS signal acquisition board. The output of NIEF is fed into the Software Defined Receiver to evaluate the acquisition and tracking performance. Experimental results shows that many types of interference such as single-tone CWI, AM, FM, swept CWI and multi-tones CWI are effectively mitigated with small signal power loss.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.7
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• pp.3227-3235
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• 2011

In this paper, a relational embedded DBMS was designed and a prototype 'Miracle' RDBMS (MDB) was developed. MDB is written in C and works on Unix, Linux and Windows platforms locally. It accesses database through SQL interfaces and API functions and uses $B^+$ tree index. It guarantees ACID in transactions and supports low concurrency control and processes SQL statements on a single table. To evaluate the performance of MDB on an ARM board EZ-S3C6410 and to compare the performance of MDB with that of SQLite, an experiment was carried out to estimate processing times for insertion, selection, update and deletion operations. The result shows that the average times for selections and insertions in MDB were 38.46% and 22.86% faster than those in SQLite, respectively, but the average times for updates and deletions in SQLite were 28.33% and 26.00% faster than MDB, respectively, This experiment shows that fetching data from database and sending data to database in MDB is faster than in SQLite, but $B^+$ tree index is implemented more effectively in SQlite than in MDB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.393-400
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• 2015

As the development and distribution of the intelligent transport system is spreading recently and some of the services are commercialized through a pilot project, interest in DSRC with high utilization is increasing and antennas for roadside and on board equipment are being studied. A single patch was used for a vehicle antenna due to the requests of miniaturization of size, but there was performance degradation in most cases due to miniaturization. In addition, some methods to improve performance have been used in the antennas that were previously researched using the arrays, but they have the disadvantages of bulkiness in size of the antennas when using the arrays. Therefore, in this paper, the CPW fed microstrip patch antenna with the simple structure of being compact and easy to produce, which can be used in the OBU of DSRC, was designed.