• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.389-392
• /
• 1999

It is essential to estimate an effective inductance in a ground plane of muliti-layer IC package system in order to determine the simultaneous switching noise of the package. A new method to estimate the effective ground inductance in multi-layer IC package is presented. With the estimated ground plane inductance values, maximum switching noise variations according to the number of simultaneously switching drivers are investigated by developing a new SSN model. These results are verified by performing HSPICE simulation with the 0.35${\mu}{\textrm}{m}$ CMOS technology.

• Journal of electromagnetic engineering and science
• /
• v.6 no.1
• /
• pp.62-70
• /
• 2006

This paper presents a new power plane design method incorporating a single geometry derived from a unit cell of photonic bandgap(PBG) structure. This method yields constantly wide suppression of parallel plate resonances from 0.9 GHz to 4.2 GHz and is very efficient to eliminate PCB resonances in a specified frequency region to provide effective suppression of simultaneous switching noise(SSN). It is shown that with only two cells the propagation of unwanted high frequency signals is effectively suppressed, while it could provide continuous return signal path. The measured results agree very well with theoretically predicted ones, and confirm that proposed method is effective for reducing EMI, with measured near-field distribution. The proposed topology is suitable for design of high speed digital system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.4
• /
• pp.302-312
• /
• 2001

As the data transfer rate between chips gets higher, both crosstalk and SSN (Simultaneous Switching Noise) deteriorate seriously the performance of a system. The proposed interface scheme uses P-CTR and N-CTR(Positive/Negative Constant Transition Rate) which encodes data at both falling and rising edges, where the transition directions of N-CTR and P-CTR are opposite. And the proposed bus system places two P-CTR drivers and two N-CTR drivers alternatively. In the proposed P/N-CTR interface scheme, the signals of neighboring interconnection lines at both sides of a bus will not switch simultaneously in the same direction, which leads to reduction in the maximum crosstalk and SSN compared to conventional interfaces. For verification of noise reduction of the proposed interface scheme, the scheme is applied to several kinds of bit-wide buses with various interconnection structures, and HSPICE simulation was performed with 0.35 ${\mu}{\textrm}{m}$ SPICE parameters. The simulation results show that in the 32-bit or less wide bus, the maximum SSN and crosstalk are reduced to at least 26.78% and 50%, respectively in comparison with the conventional interface scheme.