• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.946-949
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• 2001

Mirror surface finish of Si-wafers has been achieved by rotary in-feed machining with cup-type wheels in ELID grinding. But the diameter of the workpiece is limited with the diameter of the grinding wheel in the in-feed machining method. In this study, some grinding experiments by the rotary surface grinding machine with straight type wheels were conducted, by which the possible grinding area of the workpiece is independent of the diameter of the wheels. For the purpose of investigating the grinding characteristics of large scale diametral silicon wafer, grinding conditions such as rotation speed of grinding wheels and revolution of workpiece are varied, and grinding machine used in this experiment is rotary type surface grinding m/c equipped with an ELID unit. The surface ground using the SD8000 wheels showed that mirror like surface roughness can be attained near 2~6nm in Ra.

• New & Renewable Energy
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• v.5 no.1
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• pp.26-31
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• 2009

The surface etching characteristics of single crystalline silicon wafer were investigated using potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). The saw damage layer was removed after 10min by KOH 45wt% solution at $80^{\circ}C$. The wafer etched at high temperature ($90^{\circ}C$) and in low concentration (4wt%) of TMAH solution showed an increased etch rate of silicon wafer and wavy patterns on the surface. Especially, pyramidal textures were formed in 4wt% TMAH solution without alcohol additives.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Journal of the Semiconductor & Display Technology
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• v.12 no.3
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• pp.29-34
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• 2013

Solar cell has been considered as renewable green energy. Its silicon wafer thickness is thinner due to manufacturing cost and accordingly micro cracks is often generated in the process. Micro cracks result in bad quality of solar cell, and so their accurate and reliable detection is required. In this paper, near-infrared optics system is newly designed based on the analysis of near-infrared transmittance characteristics and its important parameters are optimally selected using the design of experiment for micro crack detection in solar cell wafer. The performance of the proposed method is verified using several experiments.

• Journal of the Korean institute of surface engineering
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• v.29 no.5
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• pp.482-486
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• 1996

The progress of microelectronics technology has been requiring agressive developments of device technologies. Also the requirements of the next generation devices is heading to the limits of their functions and materials, and hence asking the very specific silicon wafer such as SOI(Silicon On Insulator) wafer. The talk covers the dome stic and world-wide status of SOI device developments and applications. The presentation will also touch some predictions such as SOI device prgress schedules, impacts on the normal wafer developments, market sizes, SOI wafer prices, and so on. Finally it will cover technical aspects which are silicon oxide conditions for bonding, point defects and, surface contaminations. These points will be hopefully overcome by involved people in microelectronics industry.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.419-419
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• 2016

High efficiency silicon solar cell requires the textured front surface to reduce reflectance and to improve the light trapping. In case of mono-crystalline silicon solar cell, wet etching with alkaline solution is widespread. However, the alkali texturing methods are ineffective in case of multi-crystalline silicon wafer due to grain boundary of random crystallographic orientation. The acid texturing method is generally used in multi-crystalline silicon wafer to reduce the surface reflectance. However the acid textured solar cell gives low short-circuit current due to high reflectivity while it improves the open-circuit voltage. To reduce the reflectivity of multi-crystalline silicon wafer, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE experimental condition with change of RF power (100W, 150W, 200W, 250W, 300W). During experiment, the gas ratio of SF6 and O2 was fixed as 30:10.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.98-101
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• 2003

As the ultra precision grinding can be applied to wafering process by the refinement of the abrasive. the development of high stiffness equipment and grinding skill, the conventional wafering process which consists of lapping, etching, 1st, 2nd and 3rd polishing could be exchanged to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Futhermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focused on the flatness of the ground wafer. Generally, the ground wafer has concave profile because of the difference of wheel path density, grinding temperature and elastic deformation of the equiptment. Tilting mathod is applied to avoid such non-uniform material removes. So, in this paper, the geometric analysis on grinding process is carried out, and then, we can predict the profile of th ground wafer by using profile simulation.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.2 s.95
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• pp.60-67
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• 1999

Micro-fabrication techniques such as lithography and LIGA processes usually require large investment and are suitable for mass production. Therefore, there is a need for a new micro-fabrication technique that is flexible and more cost effective. In this paper a novel, economical and flexible method of producing micro-pattern on silicon wafer is presented. This method relies on selective removal of mask by mechanical cutting. Then micro-pattern is produced by chemical etching. V-shaped grooved of about 3 ${\mu}m$ wide and 2 ${\mu}m$ deep has been made on ${SiO_2}m$ coated silicon wafer with this method. This method may be utilized for making microstructures in MEMS application at low cost.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.59-60
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• 2006

The slurry stability and removal rate during recycling of slurry in silicon wafer polishing was studied. Average abrasive size of slurry was not changed with recycling time, however, large particles appeared as recycling time increased. Large particles were related foreign substances from pad or abraded silicon flakes during polishing. The removal rate as well as pH of slurry was decreased as recycling time increased. It suggests that the consumption of OH ions during recycling is the main cause of decrease of removal rate. Therefore, it is important to control pH of slurry to obtain optimum removal rate during polishing.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.4
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.