• 제목/요약/키워드: Silicon oxide substrate

검색결과 238건 처리시간 0.026초

TCO/Si 접합 EWT 태양전지에 관한 전기적 및 광학적 특성 (Electrical and Optical Properties for TCO/Si Junction of EWT Solar Cells)

  • 송진섭;양정엽;이준석;홍진표;조영현
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2010년도 추계학술대회 초록집
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    • pp.39.2-39.2
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    • 2010
  • In this work we have investigated electrical and optical properties of interface for ITO/Si with shallow doped emitter. The ITO is prepared by DC magnetron sputter on p-type monocrystalline silicon substrate. As an experimental result, The transmittance at 640nm spectra is obtained an average transmittance over 85% in the visible range of the optical spectrum. The energy bandgap of ITO at oxygen flow from 0% to 4% obtained between 3.57eV and 3.68eV (ITO : 3.75eV). The energy bandgap of ITO is depending on the thickness, sturcture and doping concentration. Because the bandgap and position of absorption edge for degenerated semiconductor oxide are determined by two competing mechanism; i) bandgap narrowing due to electron-electron and electron-impurity effects on the valance and conduction bands (> 3.38eV), ii) bandgap widening by the Burstein-Moss effect, a blocking of the lowest states of the conduction band by excess electrons( < 4.15eV). The resistivity of ITO layer obtained about $6{\times}10^{-4}{\Omega}cm$ at 4% of oxygen flow. In case of decrease resistivity of ITO, the carrier concentration and carrier mobility of ITO film will be increased. The contact resistance of ITO/Si with shallow doped emitter was measured by the transmission line method(TLM). As an experimental result, the contact resistance was obtained $0.0705{\Omega}cm^2$ at 2% oxygen flow. It is formed ohmic-contact of interface ITO/Si substrate. The emitter series resistance of ITO/Si with shallow doped emitter was obtained $0.1821{\Omega}cm^2$. Therefore, As an PC1D simulation result, the fill factor of EWT solar cell obtained above 80%. The details will be presented in conference.

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Synthesis of High-quality Graphene by Inductively-coupled Plasma-enhanced Chemical Vapor Deposition

  • Lam, Van Nang;Kumar, Challa Kiran;Park, Nam-Kyu;Arepalli, Vinaya Kumar;Kim, Eui-Tae
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2011년도 추계학술발표대회
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    • pp.16.2-16.2
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    • 2011
  • Graphene has attracted significant attention due to its unique characteristics and promising nanoelectronic device applications. For practical device applications, it is essential to synthesize high-quality and large-area graphene films. Graphene has been synthesized by eloborated mechanical exfoliation of highly oriented pyrolytic graphite, chemical reduction of exfoliated grahene oxide, thermal decomposition of silicon carbide, and chemical vapor deposition (CVD) on metal substrates such as Ni, Cu, Ru etc. The CVD has advantages over some of other methods in terms of mass production on large-areas substrates and it can be easily separated from the metal substrate and transferred to other desired substrates. Especially, plasma-enhanced CVD (PECVD) can be very efficient to synthesize high-quality graphene. Little information is available on the synthesis of graphene by PECVD even though PECVD has been demonstrated to be successful in synthesizing various carbon nanostructures such as carbon nanotubes and nanosheets. In this study, we synthesized graphene on $Ni/SiO_2/Si$ and Cu plate substrates with CH4 diluted in $Ar/H_2$ (10%) by using an inductively-coupled PECVD (ICPCVD). High-quality graphene was synthesized at as low as $700^{\circ}C$ with 600 W of plasma power while graphene layer was not formed without plasma. The growth rate of graphene was so fast that graphene films fully covered on substrate surface just for few seconds $CH_4$ gas supply. The transferred graphene films on glass substrates has a transmittance at 550 nm is higher 94%, indicating 1~3 monolayers of graphene were formed. FETs based on the grapheme films transferred to $Si/SiO_2$ substrates revealed a p-type. We will further discuss the synthesis of graphene and doped graphene by ICPVCD and their characteristics.

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$CaF_2$ 박막의 전기적, 구조적 특성 (Eelctrical and Structural Properties of $CaF_2$Films)

  • 김도영;최석원;이준신
    • 한국전기전자재료학회논문지
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    • 제11권12호
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    • pp.1122-1127
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    • 1998
  • Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

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Thermal oxidation을 이용한 결정질 실리콘 태양전지의 selective emitter 형성 방법에 대한 simulation (The Simulation of Selective Emitter Formation for Crystalline Silicon Solar Cell by Growing Thermal Oxide)

  • 최용현;손혁주;이인지;박재근;박용환
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2010년도 추계학술대회 초록집
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    • pp.53.1-53.1
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    • 2010
  • 결정질 실리콘 태양전지의 효율을 향상시키기 위하여 수광면에 서로 다른 도핑농도를 가지는 고농도 도핑영역과 저농도 도핑영역으로 이루어진 emitter를 형성하는 것이 요구되며 이를 selective emitter라 칭한다. Selective emitter를 형성하면 고농도 도핑영역에서 금속전극과 저항 접촉이 잘 형성되기 때문에 직렬 저항이 최소화되고 저농도 도핑영역에서는 전하 재결합의 감소로 인하여 태양전지의 변환효율이 상승하는 이점이 있다. Selective emitter의 형성방법은 이미 다양한 방법이 제안되고 있으나, 본 연구에서는 기존에 제시된 방법과는 다르게 열산화 시 dopant redistribution에 의한 Boron depletion 현상을 이용하여 selective emitter를 형성하는 방법을 제안하였고, 이를 Simulation을 통하여 검증하였다. 초기 emitter 확산 후 junction depth는 0.478um, 면저항은 $104.2{\Omega}/sq.$ 이었으며, nitride masking layer 두께는 0.3um로 설정하였다. $1100^{\circ}C$에서 30분간 습식산화 공정을 거친 후 nitride mask가 있는 부분의 junction depth는 1.48um, 면저항은 $89.1{\Omega}/sq$의 값을 보였고, 산화막이 형성된 부분의 junction depth는 1.16um, 면저항은 $261.8{\Omega}/sq$의 값을 보였다. 위 조건의 구조를 가진 태양전지의 변환 효율은 19.28%의 값을 나타내었고 Voc, Jsc 및 fill factor는 각각 645.08mV, $36.26mA/cm^2$, 82.42%의 값을 보였다. 한편 일반적인 구조로 설정한 태양전지의 변환 효율, Voc, Isc 및 fill factor는 각각 18.73%, 644.86mV, $36.26mA/cm^2$, 80.09%의 값을 보였다.

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저탈각 (100) Si 기판의 열산화 및 적층 결함 (Thermal oxidation and oxidation induced stacking faults of tilted angled (100) silicon substrate)

  • 김준우;최두진
    • 한국결정성장학회지
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    • 제6권2호
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    • pp.185-193
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    • 1996
  • (100) Si wafer를 $2.5^{\circ},\;5^{\circ}$ 기울인 뒤, dry $O_{2}$ 분위기에서 산화시킴으로써, 시편들 간의 산화 거동 및 산화에 의한 적층 결함 특성의 차이를 알아보았다. 시편을 $900~1200^{\circ}C$에서 산화시키고 ellipsometer로 두께를 측정한 결과 저탈각 (100) Si이 (100) Si보다 산화 속도가 빨랐으며, $5^{\circ}$ off면이 $2.5^{\circ}$ off면보다 더 빨랐다. 결정방향에 따른 산화속도 차이는 산화 온도가 높아질수록 줄어들었다. 각 시편의 속도 상수에 대한 활성화 에너지는 포물 성장 속도 상수의 경우 (100) Si, $2.5^{\circ}$ off (100) Si, $5^{\circ}$ off Si이 각각 27.3, 25.9, 27.6 kcal/mol이였고, 선형 성장 속도 상수는 58.6, 56.6, 57.4 kcal/mol이였다. 또한, 두 시편에 대해 산화막을 선택 식각하 고 광학 현미경으로 관찰하여, (100) Si에 비해 $5^{\circ}$ off된 면의 산화에 의한 적층 결함 밀도가 훨씬 낮음을 확인하였고, 적층 결함 간의 각도가 달라짐을 확인하였다.

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UV Responsive Characteristics of n-Channel Schottky Barrier MOSFET with ITO as Source/Drain Contacts

  • Kim, Tae-Hyeon;Lee, Chang-Ju;Kim, Dong-Seok;Sung, Sang-Yun;Heo, Young-Woo;Lee, Jung-Hee;Hahm, Sung-Ho
    • 센서학회지
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    • 제20권3호
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    • pp.156-161
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    • 2011
  • We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.

Removal of Anodic Aluminum Oxide Barrier Layer on Silicon Substrate by Using Cl2 BCl3 Neutral Beam Etching

  • 김찬규;연제관;민경석;오종식;염근영
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.480-480
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    • 2011
  • 양극산화(anodization)는 금속을 전기화학적으로 산화시켜 금속산화물로 만드는 기술로서 최근 다양한 크기의 나노 구조를 제조하는 기술로 각광받고 있으며, 이러한 기술에 의하여 얻어지는 anodic aluminum oxide(AAO)는 magnetic data storage, optoelectronic device, sensor에 적용될 수 있는 nano device 뿐만 아니라 nanostructure를 제조하기 위한 template 및 mask로써 최근 광범위 하게 연구되고 있다. 또한, AAO는 Al2O3의 단단한 구조를 가진 무기재료이므로 solid mask로써 다른 porous materials 보다 뛰어난 특성을 갖고 있다. 또한 electron-beam lithography 및 block co-polymer 에 의한 patterning 과 비교하여 매우 경제적이며, 재현성이 우수할 뿐만 아니라 대면적에서 나노 구조의 크기 및 형상제어가 비교적 쉽기 때문에 널리 사용되고 있다. 그러나, AAO 형성 시 생기게 되는 반구형 모양의 barrier layer는 물질(substance)과 기판과의 direct physical and electrical contact을 방해하기 때문에 해결해야 할 가장 큰 문제점 중 하나로 알려져 있다. 따라서 본 연구에서는 실리콘 기판위의 형성된 AAO의 barrier layer를 Cl/BCl3 gas mixture에서 Neutral Beam Etching (NBE)과 Ion Beam Etching (IBE) 로 각각 식각한 후 그 결과와 비교하였다. NBE와 IBE 모두 Cl2/BCl3 gas mixture에서 BCl3 gas의 첨가량이 60% 일 경우 etch rate이 가장 높게 나타났고, optical emission spectroscopy (OES)로 Cl2/BCl3 플라즈마 내의 Cl radical density와 X-ray photoelectron spectroscopy (XPS)로 AAO 표면 위를 관찰한 결과 휘발성 BOxCly의 형성이 AAO 식각에 크게 관여함을 확인 할 수 있었다. 또한, NBE와 IBE 실험한 다양한 Cl2/BCl3 gas mixture ratio 에서 AAO가 식각이 되지만, 이온빔의 경우 나노사이즈의 AAO pore의 charging에 의해 pore 아래쪽의 위치한 barrier layer를 어떤 식각조건에서도 제거하지 못하였다. 하지만, NBE에서는 BCl3-rich Cl2/BCl3 gas mixture인 식각조건에서 AAO pore에 휘발성 BOxCly를 형성하면서 barrier layer를 제거할 수 있었다.

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유기금속 화학 기상증착법으로 실리콘 기판위에 증착된 질소치환 $TiO_2$ 박막의 특성분석 (Characterization of Nitrogen-Doped $TiO_2$ Thin Films Prepared by Metalorganic Chemical Vapor Deposition)

  • 이동헌;조용수;이월인;이전국;정형진
    • 한국세라믹학회지
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    • 제31권12호
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    • pp.1577-1587
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    • 1994
  • TiO2 thin films with the substitution of oxygen with nitrogen were deposited on silicon substrate by metalorganic chemical vapor deposition (MOCVD) using Ti(OCH(CH3)2)4 (titanium tetraisopropoxide, TTIP) and N2O as source materials. X-ray diffraction (XRD) results indicated that the crystal structure of the deposited thin films was anatase TiO2 with only (101) plane observed at the deposition temperatures of 36$0^{\circ}C$ and 38$0^{\circ}C$, and with (101) and (200) plane at above 40$0^{\circ}C$. Raman spectroscopic results indicated that the crystal structure was anatase TiO2 in accordance with the XRD results without any rutile, fcc TiN, or hcp TiN structure. No fundamental difference was observed with temperature increase, but the peak intensity at 194.5 cm-1 increased with strong intensity at 143.0 cm-1 for all samples. The crystalline size of the films varied from 49.2 nm to 63.9 nm with increasing temperature as determined by slow-scan XRD experiments. The refractive index of the films increased from 2.40 to 2.55 as temperature increased. X-ray photoelectron spectroscopy (XPS) study showed only Ti 2s, Ti 2p, C 1s, O 1s and O 2s peaks at the surface of the film. The composition of the surface was estimated to be TiO1.98 from the quatitative analysis. In the bulk of the film Ti 2s, Ti 2p, O 1s, O 2s, N 1s and N 2s were detected, and Ti-N bonding was observed due to the substitution of oxygen with nitrogen. A satellite structure was observed in the Ti 2p due to the Ti-N bonding, and the composition of titanium nitride was determined to be about TiN1.0 from the position of the binding energy of Ti-N 2p3/2 and the quatitative analysis. The spectrum of Ti 2p energy level could be the sum of a 4, 5, or 6 Gaussian curve reconstruction, and the case of the sum of the 6 Gaussian curve reconstruction was physically most meaningful. From the results of Auger electron spectroscopy (AES), it was known that the composition was not varied significantly throughout the whole thickness of the film, and silicon oxide was not observed at the interface between the film and the substrate. The composition of the film was possible (TiO2)1-x.(TiN)x or TiO2-2xNx and in this experimental condition x was found to be about 0.21-0.16.

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실리콘배향에 따른 산화 속도 영향과 표면 Morphology (Effects on the Oxidation Rate with Silicon Orientation and Its Surface Morphology)

  • 전법주;오인환;임태훈;정일현
    • 공업화학
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    • 제8권3호
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    • pp.395-402
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    • 1997
  • ECR 산소 플라즈마를 사용한 건식산화법에 의해 두 가지 실리콘 배향에 대하여 실리콘 산화막을 제조한 후 Deal-Grove(D-G)모델과 Wolters-Zegers-van Duynhoven (W-Z)모델에 적용하여 시간에 따르는 막 두께의 변화를 살펴보았으며 산화속도와 산화막의 표면 morphology의 상관관계를 조사하였다. 실리콘 산화막의 두께는 Si(100)과 Si(111) 모두 반응 시간이 짧은 영역에서 선형적으로 증가하였으나 반응시간이 경과함에 따라 화학반응 속도 보다 산화막을 통과하는 반응성 라디칼들의 확산이 율속단계로 작용하여 산화속도의 증가폭이 다소 둔화되었다. D-G모델과 W-Z모델에서 확산 및 반응속도는 Si(100)보다 Si(111)이 더 큰 값을 갖기 때문에 반응속도는 1.13배 더 크게 나타났으며 이들 모델은 실험 값과 잘 일치하였다. 표면 morphology는 산화 속도가 증가해도 식각현상이 일어나지 않는 실험 조건에서 산화막의 표면 조도가 일정하였으며, 기판의 위치가 하단 전자석에 근접하고 마이크로파 출력이 증가하여 식각현상이 일어나는 실험 조건에서 표면 조도는 산화속도와 관계없이 크게 나타났다.

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Electrical Characteristic of IGZO Oxide TFTs with 3 Layer Gate Insulator

  • Lim, Sang Chul;Koo, Jae Bon;Park, Chan Woo;Jung, Soon-Won;Na, Bock Soon;Lee, Sang Seok;Cho, Kyoung Ik;Chu, Hye Yong
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.344-344
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    • 2014
  • Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

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