• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.2641-2647
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• 2003

Conventional DLLs estimate the delay times of satellite signals individually and feed back these measurements to the VCO independently. But VDLL estimates delay times and user position directly and then estimate the feedback term for VCO using the estimated position changes. In this process, input measurements are treated as vectors and these vectors are used for navigation. First advantage of VDLL is that noise is reduced in all of the tracking channels making them less likely to enter the nonlinear region and fall below threshold. Second is that VDLL can operate successfully when the conventional independent parallel DLL approach fails completely. It means that VDLL receiver can get enough total signal power to track successfully to obtain accurate position estimates under the same conditions where the signal strength from each individual satellite is so low or week that none of the individual scalar DLL can remain in lock when operating independently. To operate VDLL successfully, it needs to know the initial user dynamics and position and prevents total system from the divergence. The suggested integration method is to use the inertial navigation system to provide initial dynamics for VDLL and to maintain total system stable. We designed the GPS/INS integrated navigation system. This new type of integrated system contained the vector pseudorange format generation block, VDLL signal processing block, position estimation block and the conversion block from position change to delay time feedback term aided by INS.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.276-281
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• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

• 한국통신학회논문지
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• 제31권3A호
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• pp.214-220
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• 2006

본 논문에서는 TPC-AMS/FSS-OFDM(transmit power controlled adaptive modulated OFDM with frequency symbol spreading and equalization)시스템을 제안한다. TPC-AMS/FSS-OFDM의 송신기에서 각 S/P(serial-to-parallel)변환된 신호는 직교 확산 코드에 의해 확산 결합되어 송신하고, 수신된 신호는 수신기의 각 주파수 심볼 확산 블록에 의하여 검출되며, 같은 SINR(signal interference to noise ratio)을 얻는다. 이 때 각 주파수 심볼 확산블록에 대해서는 같은 변조 레벨과 송신 전력을 할당할 수 있다. 본 논문에서 제안한 시스템은 전체 송신 전력과 데이터 정보로 전송되는 FBI(feedback information), MLI(modulation level information)를 감소시킴으로서 전체적인 전송속도(throughput)의 성능을 개선할 수 있다.

• 전기의세계
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• 제18권6호
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• pp.33-45
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• 1969

The purpose of this paper is design the most important part of sequential control systems, that is, command-treatment part, from the signal-transformation point of view. An orderly procedure is developed by which for sequential control systems the experimental design method can be reduced to the rational design method. Important in this procedure are: 1. To make total block diagram of sequential control systems by determining input and output signals of command-treatment part. 2. To partition over-all block diagram by observing each output signal. 3. To design concretely minimum block diagram by using the operational block diagram. By applying the method for partitioning the circuit to the design, the design method for sequential control systems is organized and done rationally without the aid of experiece.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1792-1799
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• 1990

Two cases of block coded phase/frequncy modulations are investigated. minimum Euclidean distances are calculated as the function of modulation index h and rotation angle \ulcorner in the cases of 2-FSK/4-PSK and 2-FSK/8-PSK. Method of signal set partitioning is described, especially for the case of 2-FSK/8-PSK. The results are compared with S.I. Sayegh's work and shown better performance. For example, with simple parity check and repetition codes, we can get coding gain of 3 dB in the case of 2-FSK/4-PSK with block length n=4. We get 5.33 dB in the case of 2-FSK/8-PSK with n=4. And it is believed that we can get higher coding gain with proper combinations of block code and n-FSK/m-PSK type channel signal constellations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.677-680
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• 1998

In this paper, we proposed a lwo bit rate subband coding with adaptive vector quantization using the correlation between motion vector and block energy in subband. In this method, the difference between the input signal and the motion compensated interframe prediction signal is decomposed into several narrow bands using quadrature mirror filter (QMF) structure. The subband signals are then quantized by adaptive vector quantizers. In the codebook generating process, each classified region closer to the block value in the same region after the classification of region by the magnitude of motion vector and the variance values of subband block. Because codebook is genrated considering energy distribution of each region classified by motion vector and variance of subband block, this technique gives a very good visual quality at low bit rate coding.

• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.67-72
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• 2015

For the development of UFS device test system, M-PHY specifications should be matched with MIPI-standard which is analog signal protocol. In this paper, the implementation methodology and hardware structure for the M-PHY AFE (Analog Front End) Block was suggested that it can be implemented using universal components without ASIC process. The testing procedure has a jitter problem so to solve the problems we using ASIC process, normally but the ASIC process needs a lot of developing cost making the UFS device test system. In is paper, the suggestion was verified by the output signal which was compared to the MIPI-standard on the Prototype-board using universal components. The board was reduced the jitter on the condition of HS-TX and 5.824 Gbps Mode in SerDes (Serialize-deserializer). Finally, the suggestion and developed AFE block have a useful better than ASIC process on developing costs of the industrial UFS device test system.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2001년도 하계 학술대회 논문집(KISPS SUMMER CONFERENCE 2001
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• pp.177-180
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• 2001

본 논문에서는 비디오 코딩을 위한 빠른 움직임 추정(motion estimation) 방법을 제안한다. 계산량을 줄이기 위해서, 제안된 움직임 추정 알고리즘은 블록 당 탐색 점(searching point)의 수를 줄이는 대신에 프레임 당 탐색 블록(searching block)의 수를 줄임으로써 실행되어진다. 이를 위해서, 연속된 두 프레임간의 시간적인 상관관계(temporal correlation)를 통해 현재 프레임에 있는 모든 블록들을 움직임 블록(moving block)과 배경 블록(background block)으로 분류되어진다. 잘 알려진 비디오 영상들에게서 실험한 결과들을 통해 제안된 방법이 상당히 정확한 움직임 벡터(motion vector)들 뿐만 아니라 계산적인 효율성을 향상할 수 있음을 볼 수 있다.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1996년도 춘계학술대회
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• pp.240-242
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• 1996

In this paper, we proposed a method of a hearing aid suitable for the sensorineural hearing impaired. Generally as the sensorineural hearing impaired have narrow audible ranges between threshold and discomfortable level, the speech spectrum may easily go beyond their audible range. Therefore speech spectrum must be optimally amplified and compressed into the impaired's audible range. The level and frequency of input speech signal are varied continuously. So we have to make compensation input signal for frequency-gain loss of the impaired, specially in the frequency band which includes much information. The input sigaal is divided into short time block and spectrum within the block is calculated. The frequency-gain characteristic is determined using the calculated spectrum. The number of frequency band and the target gain which will be added input signal are estimated. The input signal within the block is processed by a single digital filter with the calculated frequency-gain characteristics. From the results of monosyllabic speech tests to evaluate the performance of the proposed algorithm, the scores of test were improved.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.339-342
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• 2005

In order to support ultrawide-band signal generation for low rate WPAN, several types of signal generation mechanisms are suggested such as Chaos, Impluse, and Chirp signals by the activity of IEEE 802.15.4a. The communication system applied chaos theory may have ultrawide-band characteristics with spread spectrum and immunity from multipath effect. In order to use the advantage of chaotic signal generation, we introduce the system implementation of communication and networking systems with the chaos UWB signal. This system may be composed of mainly three parts in hardware architecture : RF transmission with chaotic signal generation, signal receiver using amplifiers and filters, and 8051 & FPGA unit. The most difficult part is to implement the chaotic signal generator and build transceiver with it. The implementation of the system is devidced into two parts i.e. RF blocks and digital blocks with amplifiers, filters, ADC, 8051 processor, and FPGA. In this paper, we introduce the system block diagram for chaotic communications. Mainly the RF block is important for the system to have good performance based on the chaotic signal generator. And the main control board functions for controlling RF blocks, processing Tx and Rx data, and networking in MAC layer.