• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.4
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• pp.354-359
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• 2013

In this paper, we suggested the method for implementation of unsupervised nonlinear classification using Binary Harmony Search (BHS) algorithm, which is known as a optimization algorithm. Various algorithms have been suggested for classification of feature vectors from the process of machine learning for pattern recognition or EEG signal analysis processing. Supervised learning based support vector machine or fuzzy c-mean (FCM) based on unsupervised learning have been used for classification in the field. However, conventional methods were hard to apply nonlinear dataset classification or required prior information for supervised learning. We solved this problems with proposed classification method using heuristic approach which took the minimal Euclidean distance between vectors, then we assumed them as same class and the others were another class. For the comparison, we used FCM, self-organizing map (SOM) based on artificial neural network (ANN). KEEL machine learning datset was used for simulation. We concluded that proposed method was superior than other algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.1
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• pp.27-35
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• 2005

Ultrasonic inspection methods are widely used for detecting flaws in materials. The signal analysis step plays a crucial part in the data interpretation process. A number of signal processing methods have been proposed to classify ultrasonic flaw signals. One of the more popular methods involves the extraction of an appropriate set of features followed by the use of a neural network for the classification of the signals in the feature spare. This paper describes an alternative approach which uses the least mean square (LMS) method and exportation maximization (EM) algorithm with the model based deconvolution which is employed for classifying nondestructive evaluation (NDE) signals from steam generator tubes in a nuclear power plant. The signals due to cracks and deposits are not significantly different. These signals must be discriminated to prevent from happening a huge disaster such as contamination of water or explosion. A model based deconvolution has been described to facilitate comparison of classification results. The method uses the space alternating generalized expectation maximiBation (SAGE) algorithm ill conjunction with the Newton-Raphson method which uses the Hessian parameter resulting in fast convergence to estimate the time of flight and the distance between the tube wall and the ultrasonic sensor. Results using these schemes for the classification of ultrasonic signals from cracks and deposits within steam generator tubes are presented and showed a reasonable performances.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• Journal of the Korea Society of Computer and Information
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• v.28 no.10
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• pp.1-8
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• 2023

If there is a defect in the wheel bearing, which is a major part of the car, it can cause problems such as traffic accidents. In order to solve this problem, big data is collected and monitoring is conducted to provide early information on the presence or absence of wheel bearing failure and type of failure through predictive diagnosis and management technology. System development is needed. In this paper, to implement such an intelligent wheel hub bearing maintenance system, we develop an embedded system equipped with sensors for monitoring reliability and soundness and algorithms for predictive diagnosis. The algorithm used acquires vibration signals from acceleration sensors installed in wheel bearings and can predict and diagnose failures through big data technology through signal processing techniques, fault frequency analysis, and health characteristic parameter definition. The implemented algorithm applies a stable signal extraction algorithm that can minimize vibration frequency components and maximize vibration components occurring in wheel bearings. In noise removal using a filter, an artificial intelligence-based soundness extraction algorithm is applied, and FFT is applied. The fault frequency was analyzed and the fault was diagnosed by extracting fault characteristic factors. The performance target of this system was over 12,800 ODR, and the target was met through test results.

• Journal of Biosystems Engineering
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• v.28 no.6
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• pp.511-516
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• 2003

Computer vision technology has been utilized as one of the most powerful tools to automate various agricultural operations. Though it has demonstrated successful results in various applications, the current status of technology is still for behind the human's capability typically for the unstructured and variable task environment. In this paper, a man-machine interactive hybrid decision-making system which utilized a concept of tole-operation was proposed to overcome limitations of computer image processing and cognitive capability. Tasks of greenhouse watermelon cultivation such as pruning, watering, pesticide application, and harvest require identification of target object. Identifying water-melons including position data from the field image is very difficult because of the ambiguity among stems, leaves, shades. and fruits, especially when watermelon is covered partly by leaves or stems. Watermelon identification from the cultivation field image transmitted by wireless was selected to realize the proposed concept. The system was designed such that operator(farmer), computer, and machinery share their roles utilizing their maximum merits to accomplish given tasks successfully. And the developed system was composed of the image monitoring and task control module, wireless remote image acquisition and data transmission module, and man-machine interface module. Once task was selected from the task control and monitoring module, the analog signal of the color image of the field was captured and transmitted to the host computer using R.F. module by wireless. Operator communicated with computer through touch screen interface. And then a sequence of algorithms to identify the location and size of the watermelon was performed based on the local image processing. And the system showed practical and feasible way of automation for the volatile bio-production process.

• Geophysics and Geophysical Exploration
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• v.25 no.4
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• pp.177-188
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• 2022

Recently, the application of distributed acoustic sensors (DAS), which can replace geophones and seismometers, has significantly increased along with interest in micro-seismic monitoring technique, which is one of the CO₂ storage monitoring techniques. A significant amount of temporally and spatially continuous data is recorded in a DAS monitoring system, thereby necessitating fast and accurate data processing techniques. Because event detection and seismic phase picking are the most basic data processing techniques, they should be performed on all data. In this study, a machine learning-based P, S wave phase picking algorithm was developed to compensate for the limitations of conventional phase picking algorithms, and it was modified using a transfer learning technique for the application of DAS data consisting of a single component with a low signal-to-noise ratio. Our model was constructed by modifying the convolution-based EQTransformer, which performs well in phase picking, to the ResUNet structure. Not only the global earthquake dataset, STEAD but also the augmented dataset was used as training datasets to enhance the prediction performance on the unseen characteristics of the target dataset. The performance of the developed algorithm was verified using K-net and KiK-net data with characteristics different from the training data. Additionally, after modifying the trained model to suit DAS data using the transfer learning technique, the performance was verified by applying it to the DAS field data measured in the Pohang Janggi basin.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.312-321
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• 2003

In this paper, we implement robot which are ability to recognize obstacles and moving automatically to destination. we present two results in this paper; hardware implementation of image processing board and software implementation of visual feedback algorithm for a self-controlled robot. In the first part, the mobile robot depends on commands from a control board which is doing image processing part. We have studied the self controlled mobile robot system equipped with a CCD camera for a long time. This robot system consists of a image processing board implemented with DSPs, a stepping motor, a CCD camera. We will propose an algorithm in which commands are delivered for the robot to move in the planned path. The distance that the robot is supposed to move is calculated on the basis of the absolute coordinate and the coordinate of the target spot. And the image signal acquired by the CCD camera mounted on the robot is captured at every sampling time in order for the robot to automatically avoid the obstacle and finally to reach the destination. The image processing board consists of DSP (TMS320VC33), ADV611, SAA7111, ADV7l76A, CPLD(EPM7256ATC144), and SRAM memories. In the second part, the visual feedback control has two types of vision algorithms: obstacle avoidance and path planning. The first algorithm is cell, part of the image divided by blob analysis. We will do image preprocessing to improve the input image. This image preprocessing consists of filtering, edge detection, NOR converting, and threshold-ing. This major image processing includes labeling, segmentation, and pixel density calculation. In the second algorithm, after an image frame went through preprocessing (edge detection, converting, thresholding), the histogram is measured vertically (the y-axis direction). Then, the binary histogram of the image shows waveforms with only black and white variations. Here we use the fact that since obstacles appear as sectional diagrams as if they were walls, there is no variation in the histogram. The intensities of the line histogram are measured as vertically at intervals of 20 pixels. So, we can find uniform and nonuniform regions of the waveforms and define the period of uniform waveforms as an obstacle region. We can see that the algorithm is very useful for the robot to move avoiding obstacles.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.31-38
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• 2008

Ad-Hoc network is a network architecture which has no backbone network and is deployed temporarily and rapidly in emergency or war without fixed mobile infrastructures. All communications between network entities are carried in ad-hoc networks over the wireless medium. Due to the radio communications being extremely vulnerable to propagation impairments, connectivity between network nodes is not guaranteed. Therefore, many new algorithms have been studied recently. This study proposes the secondary header approach to the cluster based routing protocol (CBRP). The primary header becomes abnormal status so that the primary header can not participate in the communications between network entities, the secondary header immediately replaces the primary header without selecting process of the new primary header. This improves the routing interruption problem that occurs when a header is moving out from a cluster or in the abnormal status. The performances of proposed algorithm ACBRP(Advanced Cluster Based Routing Protocol) are compared with CBRP. The cost of the primary header reelection of ACBRP is simulated. And results are presented in order to show the effectiveness of the algorithm.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.51-58
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• 2002

The conventional code division multiple access(CDMA) detector shows severe degradation in communication quality as the number of users increases due to multiple access interferences(MAI). This problem thus restricts the user capacity. Various multiuser detection algorithms have been proposed to overcome the MAI problem. The existing detectors can be generally classified into one of the two categories : linear multiuser detection and subtractive interference cancellation detectors. In the linear multiuser detection, a linear transform is applied to the soft outputs of the conventional detector. In the subtractive interference cancellation detection, estimates of the interference are generated and subtracted out from the received signal. There has been great interest in the family of the subtractive interference cancellation detection because the linear multiuser detection exhibits the disadvantage of taking matrix inversion operations. The successive interference cancellation (SIC) and the parallel interference cancellation (PIC) are the two most popular structures in the subtractive interference cancellation detector. The SIC structure is very simple in hardware complexity, but has the disadvantage of increased processing delay time, while the PIC structure is good in performance, but shows the disadvantage of increased hardware complexity. In this paper we propose a mixed structure form of SIC and PIC in order to achieve good performance as well as simple hardware complexity. A performance analysis of the proposed scheme has been made, and the superior characteristics of the mixed structure are demonstrated by extensive computer simulations.