• 정보저장시스템학회논문집
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• 제1권1호
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• pp.23-28
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• 2005

This paper investigates the effects of disk thickness and Pemto slider on PES(position error signal) for high TPI(track per inch) drives above 150kTPI at early stage of their development. In order to reduce the disk flutter which becomes a dominant contributor to the TMR, the thicker disks with both 63 and 69mi1 have been used. Also, PES of a Pemto slider with thinner thickness than Pico slider has been estimated to decrease the conversion factor of disk motion in axial direction to head off-track motion. A frequency-domain PES estimation and prediction tool has been developed via measurement of disk flutter and HSA(head stack assembly) forced vibration. It has been validated by the measured PES in drive level. Based on the model and measurement of disk flutter, PES of a drive with the thicker disk and Pemto slider is predicted and their impact is investigated.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2008년도 추계학술대회 논문집
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• pp.94-97
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• 2008

In this paper, A Digital Voltage Mode Controller is designed for the Photovoltaic power converter applications. The designed Digital Voltage Mode Controller is derived analytically from the continuous time small signal model of the boost converter. Due to the small signal model based derivations of the control law, the designed control method can be applicable to K-factor Approach method and bilinear transformation. In order to show the usefulness of a designed controller, and the simulation results are verified.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.409-410
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• 2007

In this paper, we propose a new method for overlap and add synthesis using phase shaping factor in a sinusoidal synthesis method of speech signal, which improves continuity and SNR(Signal Noise Ratio) efficiency of synthesized speech.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.141-143
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• 1998

A new small-signal model for the controlled on-time boost Power factor correction (PFC) circuit is Presented. The proposed small-signal model is valid up to high frequencies ever 1kHz. IF to remove the low-frequency ripple from the output a 120Hz notch filter is used the proposed model can be used for the control design of the PFC circuit to improve the dynamics of the output voltage. The accuracy of the model is confirmed by comparing the experimental results with the simulational result.

• 산업경영시스템학회지
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• 제19권39호
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• pp.243-254
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• 1996

In this study, a model and an analysis method for parameter design is presented a linear relation between the input signal and the ideal value of a performance characteristic. Furthermore, There presented a new performance measure, expected quality loss after adjustment, which is proved to be equivalent to Taguchi's SN ratio approximately. On the basis of this, a two-step optimization procedure is proposed for parameter design considering the signal factor and the quality characteristics with continuous variable. Proposed procedure and Taguchi two-stage procedure are compared.

• Journal of the Optical Society of Korea
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• 제16권4호
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• pp.401-408
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• 2012

The amplitude error of phase modulator used in closed-loop fiber optic gyroscope has occurred by the temperature dependency of the electro-optic coefficient, and also can be due to the square-wave dither signal which is generally applied for eliminating the deadzone. This error can cause bias drift and scale factor error. This paper analyzes the temperature dependency of the modulation amplitude and the relationship with the scale factor of the gyroscope, and deals with an amplitude control method. The error calculation logic considering the dither signal is implemented on the signal processing module. The result of experiments from a prototype gyroscope shows the effect of the modulation amplitude control and a considerable improvement on performances.

• 생명과학회지
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• 제12권4호
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• pp.477-482
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• 2002

효모 glucoamylase의 promoter와 분비신호서열 그리고 MF$\alpha$1의 prosequence를 이용하여 곤충 defensin을 S. cerevisiae 2805에서 항균활성을 보유한 형태로 발현 및 분비하는데 성공하였다. 발현된 defensin의 대부분이 세포 외로 분비되어 거의 모든 항균활성이 배양 상등액에 존재하였다. 이것은 S. cerevisiae에서 발현된 defensin이 glucoamylase의 분비신호서열과 MF$\alpha$1의 prosequenre에 의해 효율적으로 processing되어 분비됨을 시사한다. Defensin의 다른 미생물에 대한 항균활성을 조사한 결과 병원균인 St. aureus와 L. monocytogenes에 대해서도 항균활성이 존재하였다.

• 한국동물학회지
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• 제33권3호
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• pp.266-275
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• 1990

Onocogene의 일종인 c-raf protein kinase는 세포질 속에 존재하는 serine / threonine-speccific protein이며, 이것은 mitogene signal에 의해 활성화된다. c-raf protein kinase의 구조와 기능은 protein kinase C와 매우 유사한 것으로 생각된다. 면역세포화학적으로 c-raf protein kinase의 signal transduction을 조사하기 위하여 EC-4 세포에 tumor promotor인 12-0-tet-radecanoylphorbol-13-acetae와 mitogenic gactor인 platelet-derived growth factor로 time-course에 따라서 처리하였다. Translocotion되는 c-raf는 먼저 perinuclear membrane에 모이고 그 후에 핵내로 이동되었다. 그런데 TPA와 PDGF로 처리한 c-raf의 translocotion은 각각의 다른 경로를 가짐을 알 수 있었다. TPA와 PAGF을 장기간 처리하였을 때, c-raf protein kinase의 down regulation이 유도됨을 알 수 있었다.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2003년도 하계학술대회 논문집
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• pp.262-267
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• 2003

At process of production according to development of accumulation degree of semi-conductor element, because functional mistake examination time required increases, is becoming big obstacle factor in cost-cutting. Studied pattern generator that generate pattern and address that is bundle enemy to process these controversial point effectively.