• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.3
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• pp.42-51
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• 1981

Boron was predeposited into p (100) Si wafer at 94$0^{\circ}C$ for 60minutes to make the back surface field. High tempreature diffusion process at 1145$^{\circ}C$ for 3 hours was immediately followed without removing boron glass to obtain high surface concentration Back boron was annealed at 110$0^{\circ}C$ for 40minutes after boron glass was removed. N+ layer was formed by predepositing with POCI3 source at 90$0^{\circ}C$ for 7~15 minutes and annealed at 80$0^{\circ}C$ for 60min1es under dry Of ambient. The triple metal layers were made by evaporating Ti, Pd, Ag in that order onto front and back of diffused wafer to form the front grid and back electrode respectively. Silver was electroplated on front and back to increase the metal thickness form 1~2$\mu$m to 3~4$\mu$m and the metal electrodes are alloyed in N2 /H2 ambient at 55$0^{\circ}C$ and followed by silicon nitride antireflection film deposition process. Under artificial illumination of 100mW/$\textrm{cm}^2$ fabricated N+PP+ cells showed typically the open circuit voltage of 0.59V and short circuit current of 103 mA with fill factor of 0.80 from the whole cell area of 3.36$\textrm{cm}^2$. These numbers can be used to get the actual total area(active area) conversion efficiency of 14.4%(16.2%) which has been improved from the provious N+P cell with 11% total area efficiency by adding P+ back.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.3
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• pp.366-376
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• 1997

$CdGa_2Se_4$, epilayer of tetragonal type are grown on Si(100) substrate by hot wall epitaxy method. The source and substrate temperature is $580^{\circ}C$ and $420^{\circ}C$ respectively, and the thickness of the film is 3 $\mu \textrm{m}$. The crystallihe structure of epilayers were investigated by double crystal X-ray diffraction(DCXD). Hall effect on this sample was measured by the method of van der Pauw and studied on carrier density and mobility depending on temperature. From Hall data, the mobility was likely to be decreased by pizoelectric scattering in the temperature range 30 K to 200 K and by polar optical scattering in the temperature range 200 K to 293 K. In order to explore of photocurrent to darkcurrent (pc/dc), maximum allowable power dissipation (MAPD), spectral response and response time. The results indicated that for the samples annealed in Se vapor the photoconductive characteristics are best. Then we obtained the sensitivity of 0.98, the value of pc/dc of $9.62{\times}10^6$, the MAPD of 321 ㎽ and the rise and decay time of 9 ㎳ and 9.5 ㎳, respectively.

• Korean Journal of Materials Research
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• v.11 no.7
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• pp.575-579
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• 2001

GaN buffer layer and epilayer have been grown on sapphire (0001) by metal organic chemical vapor deposition (MOCVD). GaN buffer layer ranging from 26 nm to 130 nm in thickness was grown at 55$0^{\circ}C$ prior to the 4 $\mu\textrm{m}$ thick GaN epitaxial deposition at 110$0^{\circ}C$. After GaN buffer layer growth, buffer layer surface was examined by atomic force microscopy (AFM). As the thickness of GaN buffer layer was increased, surface morphology of GaN epilayer was investigated by scanning electron microscopy (SEM). Double crystal X-ray diffraction (DCXRD) and Raman spectroscopy were employed to study crystallinity of GaN epilayers. Optical properties of GaN epilayers were measured by photoluminescence (PL). The epilayer grown with a thin buffer layer had rough surface, and the epilayer grown with a thick buffer layer had mirror-like surface of epilayer. Although the stress on the latter was larger than on the former, its crystallinity was much better. These results imply that the internal free energy is decreased in case of the thick buffer layer. Decrease in internal free energy promotes the lateral growth of the GaN film, which results in the smoother surface and better crystallinity.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.274-274
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• 2014

금속칼코게나이드 화합물중 하나인 $MoS_2$는 초저 마찰계수의 금속성 윤활제로 널리 사용되고 있으며 흑연과 비슷한 판상 구조를 지니고 있어 기계적 박리법을 통한 그래핀의 발견 이후 2차원 박막 합성법에 대한 활발한 연구가 진행되고 있다. 최근 다양한 응용이 진행 중인 그래핀의 경우 높은 전자이동도, 기계적 강도, 유연성, 열전도도 등 뛰어난 물리적 특성을 지니고 있으나 zero-bandgap으로 인한 낮은 on/off ratio는 thin film transistor (TFT), 논리회로(logic circuit) 등 반도체 소자 응용에 한계가 있다. 하지만 $MoS_2$는 벌크상태에서 약 1.2 eV의 indirect band-gap을 지닌 반면 단일층의 경우 1.8 eV의 direct-bandgap을 나타내고 있다. 또한 단일층 $MoS_2$를 이용하여 $HfO_2/MoS_2/SiO_2$ 구조의 트랜지스터를 제작하였을 때 $200cm^2/v^{-1}s^{-1}$의 높은 mobility와 $10^8$ 이상의 on/off ratio 나타낸다는 연구가 보고되어 있어 박막형 트랜지스터 응용을 위한 신소재로 주목을 받고 있다. 한편 2차원 $MoS_2$ 박막을 합성하기 위한 대표적인 방법인 기계적 박리법의 경우 고품질의 단일층 $MoS_2$ 성장이 가능하지만 대면적 합성에 한계를 지니고 있으며 화학기상증착법(CVD)의 경우 공정 gas의 분해를 위한 높은 온도가 요구되므로 박막형 투명 트랜지스터 응용을 위한 플라스틱 기판으로의 in-situ 성장이 어렵기 때문에 이를 보완할 수 있는 $MoS_2$ 박막 합성 공정 개발이 필요하다. 특히 Plasma enhanced chemical vapor deposition (PECVD) 방법은 공정 gas가 전기적 에너지로 분해되어 chamber 내부에서 cold-plasma 형태로 존 재하기 때문에 박막의 저온성장 및 대면적 합성이 가능하며 고진공을 바탕으로 합성 중 발생하는 오염 요소를 효과적으로 제어할 수 있다. 본 연구에서는PECVD를 이용하여 plasma power, 공정압력, 공정 gas의 유량 등 다양한 공정 변수를 조절함으로써 저온, 저압 조건하에서의 $MoS_2$ 박막 성장 가능성을 확인하였으며 전구체로는 Mo 금속과 $H_2S$ gas를 사용하였다. 또한 향후 flexible 소자 응용을 위한 플라스틱 기판의 녹는점을 고려하여 공정 온도는 $300^{\circ}C$ 이하로 설정하였으며 합성된 $MoS_2$ 박막의 두께 및 화학적 구성은 Raman spectroscopy를 이용하여 확인 하였다. 공정온도 $200^{\circ}C$와 $150^{\circ}C$에서 성장한 $MoS_2$ 박막의 Raman peak의 경우 상대적으로 낮은 공정온도로 인하여 Mo와 H2S의 화학적 결합이 감소된 것을 관찰할 수 있었고 $300^{\circ}C$의 경우 약 $26{\sim}27cm^{-1}$의 Raman peak 간격을 통해 5~6층의 $MoS_2$ 박막이 형성 된 것을 확인할 수 있었다.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.309-318
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• 2002

A stoichiometric mixture of evaporating materials for $CdIn_2S_4$ single crystal thin films was prepared from horizontal electric furnace. To obtain the single crystal thin films, $CdIn_2S_4$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by the Hot Wall Epitaxy (HWE) system. The source and substrate temperatures were $630^{\circ}C$ and $420^{\circ}C$, respectively. The crystalline structure of the single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction (DCXD). The carrier density and mobility of $CdIn_2S_4$ single crystal thin films measured with Hall effect by van der Pauw method are $9.01{\times}10^{16}\;cm^{-3}$ and $219\;cm^2/V{\cdot}s$ at 293 K, respectively. The temperature dependence of the energy band gap of the $CdIn_2S_4$ obtained from the absorption spectra was well described by the Varshni's relation, $E_g(T)=2.7116\;eV-(7.74{\times}10^{-4}\;eV)T^2/(T+434)$. The crystal field and the spin-orbit splitting energies for the valence band of the $CdIn_2S_4$ have been estimated to be 0.1291 eV and 0.0248 eV, respectively, by means of the photocurrent spectra and the Hopfield quasi cubic model. These results indicate that the splitting of the ${\Delta}so$ definitely exists in the ${\Gamma}5$ states of the valence band of the $AgInS_2$/GaAs epilayer. The three photocurrent peaks observed at 10K areascribed to the $A_1$-, $B_1$-, and C1-exciton peaks for n = 1.

• Bulletin of the Korean Chemical Society
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• v.29 no.8
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• pp.1491-1494
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• 2008

A novel platinum aminoalkoxide complex, Pt$(dmamp)_2$ has been prepared by the reaction of cis-$(py)_2PtI_2$ with two equivalents of Na(dmamp) (dmamp = 1-dimethylamino-2-methyl-2-propanolate). Single-crystal X-ray crystallographic analysis shows that the Pt(dmamp)2 complex keeps a square planar geometry with each two nitrogen atoms and two oxygen atoms having trans configuration. Platinum films have been deposited on TaN/ Ta/Si substrates by metal organic chemical vapor deposition (MOCVD) using Pt$(dmamp)_2$. As-deposited platinum thin films did not contain any appreciable amounts of impurities except a little carbon. As the deposition temperature was increased, the films resistivity and deposition rate increased. The electrical resistivity (13.6 $\mu\Omega$cm) of Pt film deposited at 400 ${^{\circ}C}$ is a little higher than the bulk value (10.5 $\mu\Omega$cm) at 293 K. The chemical composition, crystalline structure, and morphology of the deposited films were investigated by X-ray photoelectron spectroscopy, X-ray diffraction, and atomic force microscopy.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.210.1-210.1
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• 2015

최근 산화물 반도체에 대한 연구가 활발하게 이루어지고 있다. 비정질 산화물 반도체인 In-Ga-Zn-O (IGZO)는 기존의 비정질 실리콘에 비해 공정 단가가 낮으며 넓은 밴드 갭으로 인한 투명성을 가지고 있고, 저온 공정이 가능하여 다양한 기판에 적용이 가능하다. 반도체의 공정 과정에서 열처리는 소자의 특성 개선을 위해 필요하다. 일반적인 열처리 방법으로 furnace 열처리 방식이 주로 이용된다. 그러나 furnace 열처리는 시간이 오래 걸리며 일반적으로 고온에서 이루어지기 때문에 최근 연구되고 있는 유리나 플라스틱, 종이 기판을 이용한 소자의 경우 기판이 손상을 받는 단점이 있다. 이러한 단점들을 극복하기 위하여 저온 공정인 마이크로웨이브를 이용한 열처리 방식이 제안되었다. 마이크로웨이브 열처리 기술은 소자에 에너지를 직접적으로 전달하기 때문에 기존의 다른 열처리 방식들과 비교하여 에너지 전달 효율이 높다. 또한 짧은 공정 시간으로 공정 단가를 절감하고 대량생산이 가능한 장점을 가지고 있으며, 저온의 열처리로 기판의 손상이 없기 때문에 기판의 종류에 국한되지 않은 공정이 가능할 수 있을 것으로 기대된다. 따라서 본 연구에서는 마이크로웨이브 열처리가 소자의 전기적 특성 개선에 미치는 영향을 확인하였다. 제작된 IGZO 박막트렌지스터는 p-type bulk silicon 위에 thermal SiO2 산화막이 100 nm 형성된 기판을 사용하였다. RCA 클리닝을 진행한 후 RF sputter를 사용하여 In-Ga-Zn-O (1:1:1)을 70 nm 증착하였다. 이후에 Photo-lithography 공정을 통하여 active 영역을 형성하였고, 전기적 특성 평가가 용이한 junctionless 트랜지스터 구조로 제작하였다. 후속 열처리 방식으로 마이크로웨이브 열처리를 1000 W에서 2분간 실시하였다. 그리고 기존 열처리 방식과의 비교를 위해 furnace를 이용하여 N2 가스 분위기에서 $600^{\circ}C$의 온도로 30분 동안 열처리를 실시하였다. 그 결과, 마이크로웨이브 열처리를 한 소자의 경우 기존의 furnace 열처리 소자와 비교하여 우수한 전기적 특성을 나타내는 것을 확인하였다. 따라서, 마이크로웨이브를 이용한 열처리 공정은 향후 저온 공정을 요구하는 소자 공정에 활용될 수 있을 것으로 기대된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.2
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• pp.93-98
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• 2001

YMnO$_3$ films are excellent gate dielectric materials of ferroelectric random access memories (FRAMs) with MFSFET (metal -ferroelectric-semiconductor field effect transistor) structure because YMnO$_3$ films can be deposited directly on Si substrate and have a relatively low permittivity. Although the patterning of YMnO$_3$ thin films is the requisite for the fabrication of FRAMs, the etch mechanism of YMnO$_3$ thin films has not been reported. In this study, YMnO$_3$thin films were etched with Cl$_2$/Ar gas chemistries in inductively coupled plasma (ICP). The maximum etch rate of YMnO$_3$ film is 285$\AA$/min under Cl$_2$/(Cl$_2$+Ar) of 1.0, RF power of 600 W, dc-bias voltage of -200V, chamber pressure of 15 mTorr and substrate temperature of $25^{\circ}C$. The selectivities of YMnO$_3$ over CeO$_2$ and $Y_2$O$_3$ are 2.85, 1.72, respectively. The selectivities of YMnO$_3$ over PR and Pt are quite low. Chemical reaction in surface of the etched YMnO$_3$ thin films was investigated with X-ray photoelectron spectroscopy (XPS) surface of the selected YMnO$_3$ thin films was investigated with X-ray photoelectron spectroscopy(XPS) and secondary ion mass spectrometry (SIMS). The etch profile was also investigated by scaning electron microscopy(SEM)

• Progress in Superconductivity
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• v.8 no.2
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.490-490
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• 2011

Graphene, hexagonal network of carbon atoms forming a one-atom thick planar sheet, has been emerged as a fascinating material for future nanoelectronics. Huge attention has been captured by its extraordinary electronic properties, such as bipolar conductance, half integer quantum Hall effect at room temperature, ballistic transport over ${\sim}0.4{\mu}m$ length and extremely high carrier mobility at room temperature. Several approaches have been developed to produce graphene, such as micromechanical cleavage of highly ordered pyrolytic graphite using adhesive tape, chemical reduction of exfoliated graphite oxide, epitaxial growth of graphene on SiC and single crystalline metal substrate, and chemical vapor deposition (CVD) synthesis. In particular, direct synthesis of graphene using metal catalytic substrate in CVD process provides a new way to large-scale production of graphene film for realization of graphene-based electronics. In this method, metal catalytic substrates including Ni and Cu have been used for CVD synthesis of graphene. There are two proposed mechanism of graphene synthesis: carbon diffusion and precipitation for graphene synthesized on Ni, and surface adsorption for graphene synthesized on Cu, namely, self-limiting growth mechanism, which can be divided by difference of carbon solubility of the metals. Here we present that large area, uniform, and layer controllable graphene synthesized on Cu catalytic substrate is achieved by acetylene-assisted CVD. The number of graphene layer can be simply controlled by adjusting acetylene injection time, verified by Raman spectroscopy. Structural features and full details of mechanism for the growth of layer controllable graphene on Cu were systematically explored by transmission electron microscopy, atomic force microscopy, and secondary ion mass spectroscopy.