• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.938-940
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• 1999

We have fabricated SiC Schottky diode for high temperature applications. SiC thin film for drift region has been deposited by ICP-CVD. In order to establish metallization conditions, we have extracted the device parameters of the Schottky diode from the forward I-V characteristics and the C-V characteristics as a function of temperature. The ideality factor was varied from 2.07 to 1.15 and the barrier height was also varied from 1.26eV to 1.92eV with increase of temperature. The reverse blocking voltage was 183 V.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.193-198
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• 2007

The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.46.1-46.1
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• 2010

Surface passivation of crystalline silicon(c-Si) surface with a-Si:H thin films has been investigated by using quasi-steady-state photo conductance(QSSPC) measurements. Analyzing the influence of a-Si:H film thickness, process gas ratio, deposition temperature and post annealing temperature on the passivation properties of c-Si, we optimized the passivation conditions at the substrate temperature of $200-250^{\circ}C$. Best surface passivation has been obtained by post-deposition annealing of a-Si:H film layer. Post annealing around the deposition temperature was sufficient to improve the surface passivation for silicon substrates. We obtained effective carrier lifetimes above 5.5 ms on average.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.214-217
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• 2003

In this study, we prepared ZnO thin film on $SiO_2$/Si substrate by FTS (Facing Targets Sputtering) apparatus which can reduce damage on the thin film because the bombardment of high-energy Particles such as ${\gamma}$-electron can be restrained. And, properties of thin filnl grown with ZnO buffer-layer which can be suppress initial growth layer was investigated. The crystalline and the c-axis preferred orientation of ZnO thin film was also investigated by XRD. As a result, we noticed that the ZnO thin film has a good crystallographic characteristic at thickness of ZnO buffer layer 10, 20 nm and working pressure 1 mTorr.

• Solar Energy
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• v.11 no.3
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• pp.74-83
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• 1991

In this study, the (p)ZnTe/(n)Si solar cell and (n)CdS-(p)ZnTe/(n)Si poly-junction thin film are fabricated by vaccum deposition method at the substrate temperature of $200{\pm}1^{\circ}C$ and then their electrical properties are investigated and compared each other. The test results from the (p)ZnTe/(n)Si solar cell the (n)CdS-(p)ZnTe/(n)Si poly-junction thin fiim under the irradiation of solar energy $100[mW/cm^2]$ are as follows; Short circuit current$[mA/cm^2]$ (p)ZnTe/(n)Si:28 (n)CdS-(p)ZnTe/(n)Si:6.5 Open circuit voltage[mV] (p)ZnTe/(n)Si:450 (n)CdS-(p)ZnTe/(n)Si:250 Fill factor (p)ZnTe/(n)Si:0.65 (n)CdS-(p)ZnTe/(n)Si:0.27 Efficiency[%] (p)ZnTe/(n)Si:8.19 (n)CdS-(p)ZnTe/(n)Si:2.3 The thin film characteristics can be improved by annealing. But the (p)ZnTe/(n)Si solar cell are deteriorated at temperatures above $470^{\circ}C$ for annealing time longer than 15[min] and the (n)CdS-(p)ZnTe/(n)Si thin film are deteriorated at temperature about $580^{\circ}C$ for longer than 15[min]. It is found that the sheet resistance decreases with the increase of annealing temperature.

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.27-33
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• 2014

To develop high efficiency crystalline solar cells, the $SiN_x$ film for surface passivation and anti-reflection coating is very important and it is generally deposited by PECVD. In this paper, the $SiN_x$ film deposited by Hot-Wire chemical vapor deposition(HWCVD) that has no plasma damage was studied. First, to optimize the $SiN_x$ film deposition process, $SiH_4$ gas rate and substrate temperature were varied and then refractive index and thickness were measured. When $SiH_4$ gas rate was 22sccm and substrate temperature was $100^{\circ}C$, refractive index was 1.94 and higher than that of other process conditions. Second, the lifetime was measured by varying the annealing temperature and time. The annealing process was made from 5 to 30 minutes at $300{\sim}500^{\circ}C$. When the annealing temperature was $100^{\circ}C$ and time was 10minute, the lifetime was the highest. The lifetime of annealed samples was also measured after the firing process at $975^{\circ}C$. Although the lifetime of all samples was decreased by firing process, the lifetime of annealed samples before the firing process was higher than that of fired samples only. Finally, the characteristics of solar cells with HWCVD $SiN_x$ film were measured.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1514-1516
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• 1999

This paper covers our efforts to improve the low carrier mobility and light instability of hydrogenated amorphous silicon (a-Si:H) films with microcrystalline silicon $({\mu}c-Si)$ films. We successfully prepared ${\mu}c-Si$ films on $CaF_2$/glass substrate by decomposition of $SiH_4$ in RPCVD system. The $CaF_2$ films on glass served as a seed layer for ${\mu}c-Si$ film growth. The XRD analysis on $CaF_2$/glass illustrated a (111) preferred $CaF_2$ grains with the lattice mismatch less than 5 % of Si. We achieved ${\mu}c-Si$ films with a crystalline volume fraction of 61 %, (111) and (220) crystal orientations. grain size of $706\AA$, activation energy of 0.49 eV, and Photo/dark conductivity ratio of 124. By using a $CaF_2$/glass structure. we were able to achieve an improved ${\mu}c-Si$ films at a low substrate temperature of $300^{\circ}C$.

• The Korean Journal of Ceramics
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• v.6 no.2
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• pp.116-119
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• 2000

The a-axis and c-axis prefer oriented SBT thin films could be deposited on Pt(111)/Ti/$SiO_2$$650^{\circ}C$). The c-axis preferred orientation of SBT film can be obtained by Sr deficiency and high compressive stress. However, the a-axis-oriented grains can be formed under stoichiometric Sr content and nearly stress-free state.

• Transactions on Electrical and Electronic Materials
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• v.9 no.2
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• pp.73-78
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• 2008

We investigated for comparison of large-area i-a-Si:H and p-a-SiC:H film quality like thickness uniformity, optical bandgap and surface roughness using both ICP-CVD and PECVD on the large-area substrate(diameter of 100 mm). As a whole, films using ICP-CVD could be achieved much uniform thickness and bandgap of that using PECVD. For i-a-Si:H films, its uniformity of thickness and optical bandgap were 2.8 % and 0.38 %, respectively. Also, thickness and optical bandgap of p-a-SiC:H films using ICP-CVD could be obtained at 1.8 % and 0.3 %, respectively. In case of surface roughness, average surface roughness (below 5 nm) of ICP-CVD film could be much better than that (below 30 nm) of PECVD film. HIT solar cell with 2 wt%-AZO/p-a-SiC:H/i-a-Si:H/c-Si/Ag structure was fabricated and characterized with diameter of 152.3 mm in this large-area ICP-CVD system. Conversion efficiency of 9.123 % was achieved with a practical area of $100\;mm\;{\times}\;100\;mm$, which can show the potential to fabrication of the large-area solar cell using ICP-CVD method.

• Electrical & Electronic Materials
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• v.11 no.11
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• pp.22-27
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• 1998

We have investigated the effect of an ion shower doping of the laser annealed poly-Si films at an elevated substrate temperatures. The substrate temperature was varied from room temperature to 300$^{\circ}C$ when the poly-Si film was doped with phosphorus by a non-mass-separated ion shower. Optical, structural, and electrical characterizations have been performed in order to study the effect of the ion showering doping. The sheet resistance of the doped poly-Si films was decreased from7${\times}$106 $\Omega$/$\square$ to 700 $\Omega$/$\square$ when the substrate temperature was increased from room temperature to 300$^{\circ}C$. This low sheet resistance is due to the fact that the doped film doesn't become amorphous but remains in the polycrystalline phase. The mildly elevated substrate temperature appears to reduce ion damages incurred in poly-Si films during ion-shower doping. Using the ion-shower doping at 250$^{\circ}C$, the field effect mobility of 120 $\textrm{cm}^2$/(v$.$s) has been obtained for the n-channel poly-Si TFTs.