• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 1999년도 특별강연 및 추계학술발표대회 개요집
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• pp.247-250
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• 1999

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 추계 기술심포지움 논문집
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• pp.75-78
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• 2000

• 한국재료학회:학술대회논문집
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• 한국재료학회 2002년도 추계학술발표강연 및 논문개요집
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• pp.48-48
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• 2002

• 한국재료학회지
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• 제12권6호
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• pp.508-512
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• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.27.1-27.1
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• 2011

The recent extensive research of one-dimensional (1D) nanostructures such as nanowires (NWs) and nanotubes (NTs) has been the driving force to fabricate new kinds of nanoscale devices in electronics, optics and bioengineering. We attempt to produce silicon oxide nanowires (SiOxNWs) in a simple way without complicate deposition process, gaseous Si containing precursors, or starting material of $SiO_2$. Nickel (Ni) nanoparticles (NPs) were applied on Si wafer and thermally treated in a furnace. The temperature in the furnace was kept in the ranges between 900 and $1,100^{\circ}C$ and a mixture of nitrogen ($N_2$) and hydrogen ($H_2$) flowed through the furnace. The SiOxNWs had widths ranging from 100 to 200 nm with length extending up to ~10 ${\mu}m$ and their structure was amorphous. Ni NPs were acted as catalysts. Since there were no other Si materials introduced into the furnace, the Si wafer was the only Si sources for the growth of SiOxNWs. When the Si wafer with deposition of Ni NPs was heated, the liquid Ni-Si alloy droplets were formed. The droplets as the nucleation sites induce an initiation of the growth of SiOxNWs and absorb oxygen easily. As the droplets became supersaturated, the SiOxNWs were grown, by the reaction between Si and O and continuously dissolving Si and O onto NPs. Photoluminescence (PL) showed that blue emission spectrum was centered at the wavelength of 450 nm (2.76 eV). The details of growth mechanism of SiOxNWs and the effect of Ni NPs on the formation of SiOxNWs will be presented.

• 한국전기전자재료학회논문지
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• 제16권4호
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• 한국결정성장학회지
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• 제20권5호
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• pp.216-220
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• 2010

Si(100) wafer와 $SiO_2$/Si(100) 웨이퍼에 증착된 NiFe 합금 박막의 결정상과 자기적 특성을 비교하고자 동시 스퍼터링법을 이용하여 두 기판 위에 150 nm의 박막을 제조하여 그의 상변화와 자기적 특성을 XRD, FE-SEM, VSM으로 비교하였다. 두 기판 위에 증착된 NiFe 박막은 BCC상으로 증착되었으나 $400^{\circ}C$에서 2시간 열처리를 한 결과 BCC에서 FCC로의 상전이가 일어나는 것을 관찰 할 수 있었으며 Si(100) wafer위에 증착된 박막에서는 $500^{\circ}C$에서 열처리 후에도 BCC와 FCC가 혼재하여 나타나는 것을 알 수 있었다. $450^{\circ}C$에서 열처리 하였을 때 각형비가 가장 높았으며 포화자화는 0.0118 emu로 나타나고 있었다. $500^{\circ}C$ 이상의 온도에서는 상전이로 인해 포화자화가 급격히 감소하는 것을 볼 수 있었다.

• 센서학회지
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• 제9권2호
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• pp.134-140
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• 2000

Si기판 직접접합기술은 전자소자 및 MEMS에의 응용에 있어 대단히 매력적인 기술이다. 본 논문에서는 Si기판 직접접합에 있어서 HF 전처리 조건에 따른 초기접합에 관하여 서술한다. 접합된 시료들의 특성은 HF 농도, 인가하중과 같이 각각의 접합조건하에서 분석하였으며, 접합력은 인장강도측정법에 의해 평가하였다. 계면상의 결합성분과 표면의 거칠기는 FT-IR과 AFM을 사용하여 평가하였다. HF 전처리 후 Si기판 표면상의 Si-F결합은 DI water에 세정하는 동안 Si-OH로 재배열되며, 결과적으로 hydrophobic 기판은 Si-OH$\cdots$(HOH$\cdots$HOH$\cdots$HOH)$\cdots$OH-S의 수소결합되어 hydrophilic화된다. 초기접합력은 초기접합전의 HF 전처리 조건에 의존한다. (최소 : $2.4kgf/cm^2{\sim}$최대 : $14.9kgf/cm^2$)

• 한국전기전자재료학회논문지
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• 제15권6호
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• pp.479-485
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• 2002

We have investigated the effects of various wafers cleaning on glass/Si bonding using 4 inch Pyrex glass wafers and 4 inch silicon wafers. The various wafer cleaning methods were examined; SPM(sulfuric-peroxide mixture, $H_2SO_4:H_2O_2$ = 4 : 1, $120^{\circ}C$), RCA(company name, $NH_4OH:H_2O_2:H_2O$ = 1 : 1 : 5, $80^{\circ}C$), and combinations of those. The best room temperature bonding result was achieved when wafers were cleaned by SPM followed by RCA cleaning. The minimum increase in surface roughness measured by AFM(atomic force microscope) confirmed such results. During successive heat treatments, the bonding strength was improved with increased annealing temperatures up to $400^{\circ}C$, but debonding was observed at $450^{\circ}C$. The difference in thermal expansion coefficients between glass and Si wafer led debonding. When annealed at fixed temperatures(300 and $400^{\circ}C$), bonding strength was enhanced until 28 hours, but then decreased for further anneal. To find the cause of decrease in bonding strength in excessively long annealing time, the ion distribution at Si surface was investigated using SIMS(secondary ion mass spectrometry). tons such as sodium, which had been existed only in glass before annealing, were found at Si surface for long annealed samples. Decrease in bonding strength can be caused by the diffused sodium ions to pass the glass/si interface. Therefore, maximum bonding strength can be achieved when the cleaning procedure and the ion concentrations at interface are optimized in glass/Si wafer direct bonding.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.360-361
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• 2005

Rapid progress in IC fabrication technology has strong demand in polishing of silicon wafer to meet the tight specification of nanotopography and surface roughness. One of the important issues in Si CMP is the stabilization of polishing pad. If a polishing pad is not stabilized before main Si wafer polishing process, good polishing result can not be expected. Therefore, new pad must be subjected into break-in process using dummy wafers for a certain period of time to enhance its performance. After the break-in process, the main Si wafer polishing process must be performed. In this study, the characteristics of break-in process were investigated in Si wafer polishing. Viscoelastic behavior, temperature variation of pad and friction were measured to evaluate the break-in phenomenon. Also, it is found that the characteristic of the break-in seems to be related to viscoelastic behavior of pad.