• Proceedings of the KIEE Conference
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• summer
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• pp.485-487
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• 2004

High-voltage gas-insulated circuit-breaker must interrupt short-circuit current successfully when breakdown occurs in electric power system. Among many test-duties, Basic Terminal fault T100a(BTF T100a) is the one of the severest duties because of its high DC component of short-circuit current. In this paper, we developed 245kV 50kA gas circuit breaker using control circuits to reduce DC component while interrupting short-circuit current, then got good performance through high-power tests in Korea Electrotechnology Research Institute(KERI) and KEMA

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.286-290
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• 2001

This paper describes an improved short-circuit protection method with a boost type rectifier using a multilevel ac/dc power converter. The output dc power of the proposed converter can be disconnected from the load within several hundred microseconds at the instant of short-circuit fault. Once the fault has been cleared the dc power is reapplied to the load. The rising time of the dc load voltage is as small as several hundred microseconds, and there is no overshoot of the dc voltage because the dc output capacitors hold undischarged state. The converter, which employs the proposed method, has the characteristics of a simplified structure, reduced cost, weight, and volume compared with a conventional power supply, which has frequent output short-circuits. Experimental results are presented to verify the usefulness of the proposed converter.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.1
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• pp.101-106
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• 2011

The failure of cooling system in Superconducting Fault Current Limiter(SFCL) increases the impedance of superconducting device, and due to malfunction of inner switches the SFCL opens the distribution system inadvertently when required to do so. In this paper, the ground fault and short circuit fault were classified as active failure and the open circuit fault was passive failure. A reliability model of SFCL considers the passive failure as well as active failure, and in the case study the reliability indices of distribution system are evaluated. It is possible that the reliability evaluation excluded passive failure makes the customers reliability seem so worse than it really was. Therefore, the reliability models of SFCL must include the active failure and passive failure together to evaluate the reliability of distribution system connected SFCL.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.272-273
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• 2015

This paper analyze scenario of feeder wire fault that occurs in the AC feeding system considering train position. The fault location of AC feeding system is calculated by measuring impedance. However, in this way, estimation error can be occurred because of tie connection, boosting current, etc. Therefore, it's hard to find fault location, so that it is required to detailed circuit analysis according to fault location. We analyze the short circuit impedance values with respect to feeder wire fault according to a train position. In this paper, PSCAD is used for modeling and analysis of AC railway feeding system.

• Transactions on Electrical and Electronic Materials
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• v.18 no.3
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• pp.159-162
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• 2017

In designing the autotransformer type superconducting fault-current limiter (SFCL), one must consider that the iron core can be saturated for the SFCL to have effective fault-current limiting operation. In this paper, to examine the saturation of the iron core comprising SFCL during the fault period, the linkage flux and the magnetizing current of the SFCL were derived from the electrical equivalent circuit with the nonlinear exciting branch. By analysis on the linkage flux versus the magnetizing current of the autotransformer type SFCL, calculated from the short-circuit tests, the design condition for the suppression of the iron core's saturation was discussed.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.4
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• pp.533-542
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• 1994

This paper presents the new algorithm for fault analysis and this algorithm obtains requisite term for fault analysis by the two-port network technique. Therefore, the fault calculation time is composed of only few fundamental arithmetic calculation. The graphic user environment for fault analysis is implemented in mouse-oriented user interface with window and pull-down menu. The result of the algorithm proved to be identical with the sample system in Ref.[8]. this package can be a useful tool for fault analysis.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.371-373
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• 2005

An enhancement for a transmission and substation equipment in power system make the system impedance to be lower. In principle, if the system impedance become low, system stability will be better, but the fault current become very higher. It is a very big problem for CB operating. As a fact of CB operating performance, high amplitude of the fault current may cause CB operation failure because of exceeding standard value in TRV. So we simulated TRV by using the EMTP. Generally there are two types of TRV in actual power system. One is short line fault, the other is bus terminal fault. In this paper, we simulated the TRv at short line fault as installed current limit reactors to reduce fault current in 345kV ultra-high voltage system. Short line fault is caused from single line fault in transmission line.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1097-1109
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• 2016

Fault detection and isolation are related to system monitoring, identifying when a fault has occurred, and determining the type of fault and its location. Fault detection is utilized to determine whether a problem has occurred within a certain channel or area of operation. Fault detection and diagnosis have become increasingly important for many technical processes in the development of safe and efficient advanced systems for supervision. This paper presents an integrated technique for fault diagnosis and classification for open- and short-circuit faults in three-phase inverter circuits. Discrete wavelet transform and principal component analysis are utilized to detect the discontinuity in currents caused by a fault. The features of fault diagnosis are then extracted. A fault dictionary is used to acquire details about transistor faults and the corresponding fault identification. Fault classification is performed with a fuzzy logic system and relevance vector machine (RVM). The proposed model is incorporated with a set of optimization techniques, namely, evolutionary particle swarm optimization (EPSO) and cuckoo search optimization (CSO), to improve fault detection. The combination of optimization techniques with classification techniques is analyzed. Experimental results confirm that the combination of CSO with RVM yields better results than the combinations of CSO with fuzzy logic system, EPSO with RVM, and EPSO with fuzzy logic system.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1540-1541
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• 2006

For limitation and interruption of short circuit currents from low voltage to extra high voltage applications, the electrical equipment including fuses and circuit breakers, are widely used today. But in order to anticipate increasing needs for effective and competitive device for limiting the growing fault current in electrical power systems, fault current limitation technologies and fault current limitation devices are widely introduced and investigated in these days. Fault current limiters are emerging electric equipment which is under development using various methods including superconducting fault current limiter, solid state fault current limiter, arc driving fault current limiters. And these various methods have some advantages and disadvantages to take into considerations In order to commercialize fault current limiters in the electrical networks, a lot of discussions should be given on the point that fault current limiting methods, need for fault current limiters, coordination with existing protective system, and field experience before commercialization. In this paper, recent trends of fault current limiting technologies will be reviewed and the key issues of superconducting fault current limiters will be dealt with. And finally, future applications of superconducting fault current limiters would be discussed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.