• Journal of IKEEE
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• v.17 no.3
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• pp.352-359
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• 2013

This paper proposes an entropy coding unit for H.264/AVC baseline profile. Entropy coding requires code tables for macroblock encoding. There are patterns in codewords of each code tables. In this paper, the patterns between codewords are analyzed to reduce the hardware cost. The entropy coding unit consists of Exp-Golomb unit and CAVLC unit. The Exp-Golomb unit can process five code types in a single unit. It can perform Exp-Golomb processing using only two adders. While typical CAVLC units use various code tables which require large amounts of resources, the sizes of the tables are reduced to about 40% or less of typical CAVLC units using relationships between table elements in the proposed CAVLC unit. After the Exp-Golomb unit and the CAVLC unit generate code values, the entropy unit uses a small size shifter for bit-stream generation while typical methods are barrel shifters.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.59-65
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• 1999

In this paper, we design a entorpy encoder of HDTV/DTV encoder blocks on the basis of MPEG-II. The designed entropy encoder outputs its bit stream at 9Mbps bit rate inserting zero-stepping block to protect the depletion of buffer in case that the generated bit stream is stored in buffer and uses not only PROM bit combinational circuit to solve the problem of critical path, and packer block, one of submerge, is designed to packing into 24 bit unit using barrel shifter, and it is constructed to blocks of header information encoder, input information delay, submerge, and buffer control. Designed circuits is verified by VHDL function simulation, as a result of performing P&R with Gate compiler that apply $0.8{\mu}m$ Gate Array specification, pin and gate number of total circuits has been tested to each 235 and about 120,000.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.3
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• pp.1-6
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• 2008

A dual band I/Q modulator which converts baseband input signals to 2.4GHz or 5GHz RF output has been proposed. The dual band I/Q modulator for 2.4GHz and 5GHz wireless LAN applications consists of $90^{\circ}$ phase shifter and wideband mixer. The I/Q modulator showed 15dB conversion loss at 2.4GHz and 16dB conversion loss at 5GHz. The sideband suppression is about 15dBc at 2.4GHz and 16dBc at 5GHz. Measured data shows 8.5% EVM at 2.4GHz, and 10% EVM at 5GHz for QPSK with symbol rate of 11Mbps. A carrier rejection is about 40dBc at 2.4GHz/5GHz band, and the I/Q modulator satisfied the output wireless LAN spectrum mask with baseband input signal.

• Korean Journal of Optics and Photonics
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• v.15 no.6
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• pp.591-596
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• 2004

In this paper, a photonic RF true-time delay based on a partially side-polished fiber Bragg grating with heating electrode has been proposed and fabricated. It features continuous voltage-controlled operation, requiring no mechanical perturbation and no moving parts. For an RF signal carried over an optical signal, the time delay has been obtained by controlling the voltage applied to the electrode and thus adjusting its reflection positions from the fiber grating via the thermooptic effect. The achieved time delay is about 100 ps with the electrical power consumption of 280 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.53-59
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• 2006

This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.53-58
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• 2008

This paper proposes a new set of instructions to improve the packet processing capacity of a network processor. The proposed set of instructions is able to achieve more efficient packet processing by accelerating integration of packet headers. Furthermore, a hardware configuration dedicated to processing overlay instructions was designed to reduce additional hardware cost. For this purpose, the basic architecture for the network processor was designed using LISA and the overlay block was optimized based on the barrel shifter. The block was synthesized to compare the area and the operation delay, and allocated to a C-level macro function using the compiler known function (CKF). The improvement in performance was confirmed by comparing the execution cycle and the execution time of an application program. Experiments were conducted using the processor designer and the compiler designer from Coware. The result of synthesis with the TSMC ($0.25{\mu}m$) from Synopsys indicated a reduction in operation delay by 20.7% and an improvement in performance of 30.8% with the proposed set of instructions for the entire execution cycle.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.661-670
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• 2013

In this paper, we propose the measurement techniques of mixed waveform. Mixed waveform has phase-continuous periodic waveform with fixed frequency signal and Linear Frequency Modulation(LFM) signal. This waveform is generated from a compact radar transmitter with frequency synthesizer and high power amplifier. Frequency synthesizer generates various signal waveform with continuos phase and high power amplifier amplify transmitting signal. First, we describe a compact radar transmitter with the phase-continuos signal and then verify the distortion characteristic of pulse compression by the mismatch of LFM waveform. Second, we describe three kinds of measurement techniques for measuring LFM waveform. These techniques include methods using signal analyzer, signal source analyzer and new methods using RF mixer and phase shifter. Finally, we verify the accuracy of the measurement technique from the pulse compression result of receiving signal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.913-920
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• 2017

In this development, By using the phase array antenna, the beam around was electronically revolved and the marine fixed type radar of which the detection is possible was made and the check around was tested. There are the risk of the corrosion because of the abrasion of the axis of rotation and salinity with the way that the existing marine pulse radar detects the check by using the mechanical rotation. Besides, the maintenance cost of the magnetron gets to happen by using the detection signal. In this development, The fixed type radar of the low output which revolves electronically around the beam by using the radar signal processing method of the phase array antenna using the phase shifter and FMCW(Frequency Modulation Continuous Wave) method was made. And by using the fixed type radar, the check detection test was conducted.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.301-306
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• 2014

We proposed a new PCB-type 'common-mode current($I_c$) and differential-mode current($I_d$) detector' working for fast detection of $I_c$ and $I_d$ from the differential-mode signaling, with miniaturization effect and possibility of cheaper fabrication. In order to realize this device, we suggest a branch-line-coupler balun having a composite right- and left-handed(CRLH) one-layer microstrip phase-shifting line as compact as roughly ${\lambda}_g/14$. The presented balun obviously is different from the conventional bent-&-folded delay lines or slits on the ground for coupling the lines on the top and bottom dielectrics. As we connect the suggested balun output ports of the differential-mode signal lines via the through-port named U and coupled-port named L, $I_c$ and $I_d$ will appear at port ${\Delta}$ and port ${\Sigma}$ of the present device, in order. The validity of the design scheme is verified by the circuit-and numerical electromagnetic analyses, and the dispersion curve proving the metamaterial characteristics of the geometry. Besides, the examples of the $I_c$ and $I_d$ indicator are observed as the even and odd modes in differential-mode signal feeding. Also, the proposed device is shown to be very compact, compared with the conventional structure.

• Convergence Security Journal
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• v.7 no.2
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• pp.73-80
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• 2007

The fact that since Internet has been spreaded widely to people, Many security problems also have been grown too much. Due to sudden growth, administrator's responsibility for secure network and services has been growing more and more. This paper represents how to prevent account which didn't use for long period on multi domains environment using service log analysis. hence administrator can find security hole on systems and can dealing with it. The Service Log Analyzer is that loading log file which are written by each service and analyzing them. as a result it makes a list named Used User List contains a number of account names which uses specific services. When the time has come - means cron job schedule time, User Usage Shifter is the next runner. it's mission is finding the person who didn't used service for a specific period of time. Then modifying the expire day of the account information.