• The Journal of Korean Institute of Communications and Information Sciences
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• 제29권1C호
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• pp.119-128
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• 2004

In this paper, a low-power 8-point DCT structure is proposed using add and shift operations. Proposed structure adopts 4 cycles for complete 8-point DCT in order to minimize size of hardware and to enable high-speed processing. In the structure, hardware for the first cycle can be shared in the next 3 cycles since all columns in the DCT coefficient matrix are common except sign. Conventional DCT structures implemented with only add and shift operation use CSD(Canonic Signed Digit) form coefficients to reduce the number of adders. To reduce the number of adders further, we propose a new structure using common sub-expression sharing techniques. With this techniques, the proposed 8-point DCT structure achieves 19.5% adder reduction comparison to the conventional structure using only CSD coefficient form.

• Journal of the Institute of Convergence Signal Processing
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• 제11권1호
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• pp.41-46
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• 2010

In this paper, the DoA(Direction of Arrival) estimator using unitary MUSIC algorithm is studied. The complex-valued correlation matrix of MUSIC algorithm is transformed to the real-valued one using unitary transform for easy implementation. The eigenvalue and eigenvector are obtained by the combined Jacobi-CORDIC algorithm. CORDIC algorithm can be implemented by only ADD and SHIFT operations and MUSIC spectrum computed by 256 point DFT algorithm. Results of unitary MUSIC algorithm designed by System Generator for FPGA implementation is entirely consistent with Matlab results. Its performance is evaluated through hardware co-simulation and resource estimation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제23권6호
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• pp.55-60
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• 2023

When performing the multiplication m×r=p of two binary numbers m and r on a computer, there is a shift-and-add(SA) method in which no time-consuming multiplication is performed, but only addition and shift-right(SR). SA is a very simple method in which when the value of the multiplier r_i is 0, the result p is only SR with m×0=0, and when r_i is 1, the result p=p+m is performed with m×1=m, and p is SR. In SA, the number of SRs can no longer be shortened, and the improvement part is whether the number of additions is shortened. This paper proposes an SA method to minimize addition based on the fact that setting a smaller number to r when converted to a binary number to be processed by a computer can significantly reduce the number of additions compared to the case of setting a smaller number to r based on the decimals that humans perform. The number of additions to the proposed algorithm was compared for four cases with signs (-,-), (-,+), (+,-), and (+,+) for some numbers in the range [-127,128]. The conclusion obtained from the experiment showed that when determining m and r, it should be determined as a binary number rather than a decimal number.

• Journal of the Korea Institute of Military Science and Technology
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• 제16권5호
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• pp.613-621
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• 2013

This paper presents the direction finding proximity fuze sensor using the clutter rejection method and the adaptive target detection algorithm for anti-air missiles. To remove effects by clutter and detect a target accurately, the clutter rejection method of Legendre sequence with BPSK(Bi phase Shift Keying) modulation has been proposed and the Doppler signal which has cross correlation characteristics is obtained from reflected target signals. Considering the change of the Doppler signal, the adaptive target detection algorithm has been developed and the direction finding algorithm has been fulfilled by comparing received powers from adjacent three receiving antennas. The encounter simulation test apparatus was made to collect and analyze reflected signal and test results showed that the -10 dBsm target was detected over 10 meters and the target with mesh clutter was detected and direction was distinguished definitely.

• Journal of the Korea Institute of Military Science and Technology
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• 제16권1호
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• pp.81-88
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• 2013

This paper describes the fundamentals, design, realization and test results of a BPSK(Bi Phase Shift Keying) transceiver for the direction finding proximity fuze sensor for anti-aircrafts or air missiles. The BPSK transceiver for the direction finding fuze sensor has been designed to detect a moving target by Doppler signal processing with the code correlation method and to distinguish direction by comparing received powers of each Doppler signal from adjacent three receiving antennas. The electrical and ESS(Environmental Stress Screening) tests of the BPSK transceiver showed satisfactory results and target detection and direction finding performances proved to be successful through dynamic operation tests by 155 mm gun firing.

• Journal of the Korean Institute of Telematics and Electronics B
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• 제28B권7호
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• pp.520-534
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• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.

• Archives of Pharmacal Research
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• 제14권1호
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• pp.35-40
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• 1991

(R) (+) and (S) (-) $4-^2H$-phenytoin have been used as substrates for the determination of the percentage of deuterium retention (NIH shift) after para-hydroxylation of the substrates in rat. By using GC-MS analyses, the percentages of deuterium retention were found to be 69% and 70% for the (R) and (S) phenyl rings, respectively. The results add additional evidence for the involvement of arene oxide in the oxidation of the pro (R) and pro (S) phenyls of phenytoin. The oxidation process of each ring could be mediated by independent enzyme systems, a rapid oxidative enzyme for the pro (S) phenyl and a slow oxidative enzyme for the pro (R) phenyl.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.305-308
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• 2001

This paper describes the design of elliptic curve cryptographic (ECC) coprocessor over binary fields for the If card. This coprocessor is implemented by the shift-and-add algorithm for the field multiplication algorithm. And the modified almost inverse algorithm(MAIA) is selected for the inverse multiplication algorithm. These two algorithms is merged to minimize the hardware size. Scalar multiplication is performed by the binary Non Adjacent Format(NAF) method. The ECC we have implemented is defined over the field GF(2$^{163}$), which is a SEC-2 recommendation［7］..

• Proceedings of the IEEK Conference
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.236-239
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• 1999

This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제21권7호
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• pp.1267-1275
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• 2017

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.