• Title/Summary/Keyword: Shift algorithm

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Output Voltage Control Technique Using Current Forward Compensation for Phase Shifted Full Bridge Converter Without Output Capacitor (출력 커패시터가 없는 위상천이 풀브릿지 컨버터의 전류 전향 보상을 이용한 출력 전압 제어 기법)

  • Shin, You-Seung;Baek, Seung-Woo;Kim, Hag-Wone;Cho, Kwan-Yual;Kang, Jeong-Won
    • The Transactions of the Korean Institute of Power Electronics
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    • v.27 no.1
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    • pp.40-47
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    • 2022
  • At present, the low-voltage, high-current type power supply is mainly used for effective sterilization in the ballast water treatment system. Research on PSFB converters without output capacitors has been ongoing. Such converters effectively treat ballast water without a separate disinfectant through electric pulses by applying a pulse-type power to the output electrode without an output capacitor. However, in the case of the pulse-type electrolysis treatment method, voltage overshoot can occur due to abrupt voltage fluctuations when the load changes, resulting in circuit reliability problems because of the output capacitorless system. Therefore, a new voltage control algorithm is required. In this paper, we will discuss voltage control for pulsed electrolysis topology without an output capacitor. The proposed voltage control method has been verified using Simulation and experiment. The usefulness of the proposed control method has been proven by the experimental results.

A Study on the Application of Measurement Data Using Machine Learning Regression Models

  • Yun-Seok Seo;Young-Gon Kim
    • International journal of advanced smart convergence
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    • v.12 no.2
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    • pp.47-55
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    • 2023
  • The automotive industry is undergoing a paradigm shift due to the convergence of IT and rapid digital transformation. Various components, including embedded structures and systems with complex architectures that incorporate IC semiconductors, are being integrated and modularized. As a result, there has been a significant increase in vehicle defects, raising expectations for the quality of automotive parts. As more and more data is being accumulated, there is an active effort to go beyond traditional reliability analysis methods and apply machine learning models based on the accumulated big data. However, there are still not many cases where machine learning is used in product development to identify factors of defects in performance and durability of products and incorporate feedback into the design to improve product quality. In this paper, we applied a prediction algorithm to the defects of automotive door devices equipped with automatic responsive sensors, which are commonly installed in recent electric and hydrogen vehicles. To do so, we selected test items, built a measurement emulation system for data acquisition, and conducted comparative evaluations by applying different machine learning algorithms to the measured data. The results in terms of R2 score were as follows: Ordinary multiple regression 0.96, Ridge regression 0.95, Lasso regression 0.89, Elastic regression 0.91.

Active and Passive Beamforming for IRS-Aided Vehicle Communication

  • Xiangping Kong;Yu Wang;Lei Zhang;Yulong Shang;Ziyan Jia
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.17 no.5
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    • pp.1503-1515
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    • 2023
  • This paper considers the jointly active and passive beamforming design in the IRS-aided MISO downlink vehicle communication system where both V2I and V2V communication paradigms coexist. We formulate the problem as an optimization problem aiming to minimize the total transmit power of the base station subject to SINR requirements of both V2I and V2V users, total transmit power of base station and IRS's phase shift constraints. To deal with this non-convex problem, we propose a method which can alternately optimize the active beamforming at the base station and the passive beamforming at the IRS. By using first-order Taylor expansion, matrix analysis theory and penalized convex-concave process method, the non-convex optimization problem with coupled variables is converted into two decoupled convex sub-problems. The simulation results show that the proposed alternate optimization algorithm can significantly decrease the total transmit power of the vehicle base station.

On the Optimal Allocation of Labour Gangs in the Port (항만하역 노동력의 효율적인 배분에 관하여)

  • Lee, Cheol-Yeong;Woo, Byung-Goo
    • Journal of Korean Port Research
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    • v.1 no.1
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    • pp.21-47
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    • 1987
  • Nowaday all the countries of the world have studied the various problems caused in operating their own ports efficiently. Ship delay in the port is attributal to the inefficient operation in the navigation aids, the cargo handling, the storage and transfer facilities, and to the inefficient allocation of gangs or to a bad service for ships. Among these elements the allocation of gangs is the predominating factor in minimizing ship's turn round time. At present, in the case of Pusan Port. the labour union and stevedoring companies allocate gangs in every hatches of ships by a rule of thumb, just placing emphasis on minimizing ship's turn round time, without applying the principle of allocation during the cargo handling. Owing to this the efficiency of the cargo handling could not be expected to be maximized and this unsystematic operation result in supplying human resources of much unnecessary surplus gangs. Therefore in this paper the optimal size and allocation of gangs for minimizing the ship's turn round time is studied and formularized. For the determination of the priority for allocation the evaluation function, namely $F=PHi^{n}{\times}(W+H)$, can be obtained; where, PHI : Principal Hatch Index W : Total Cargo Weight represented in Gang-Shifts H : Total Number of Ship's hatches and also for the optimal size of gangs the average number of gang allocated per shift (Ng), namely Ng=W/PHI, is used. The proposed algorithm is applied to Pusan Port and its validity is verified.

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A Study on the Fast Computational Algorithm for the Discrete Cosine Transform(DCT) via Lifting Scheme (리프팅 구조를 경유한 고속의 DCT 계산 알고리즘에 관한 연구)

  • Inn-Ho Jee
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.23 no.6
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    • pp.75-80
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    • 2023
  • We show the design of fast invertible block transforms that can replace the DCT in future wireless and portable computing application. This is called binDCT. In binDCT, both the forward and the inverse transforms can be implemented using only binary shift and addition operation. And the binDCT inherits all desirable DCT characteristics such as high coding gain, no DC leakage, symmetric basis functions, and recursive construction. The binDCT also inherits all lifting properties such as fast implementations, invertible integer-to-integer mapping, in-place computation. Thus, this method has advantage of fast implementation for complex DCT calculations. In this paper, we present computation costs and performance analysis between DCT and binDCT using Shapiro's EZW.

Development of a New Lunar Regolith Simulant using an Automated Program Framework

  • GyeongRok Kwon;Kyeong Ja Kim;Eungseok Yi
    • Journal of Astronomy and Space Sciences
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    • v.41 no.2
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    • pp.79-85
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    • 2024
  • Nowadays, the trend in lunar exploration missions is shifting from prospecting lunar surface to utilizing in-situ resources and establishing sustainable bridgehead. In the past, experiments were mainly focused on rover maneuvers and equipment operations. But the current shift in trend requires more complex experiments that includes preparations for resource extraction, space construction and even space agriculture. To achieve that, the experiment requires a sophisticated simulation of the lunar environment, but we are not yet prepared for this. Particularly, in the case of lunar regolith simulants, precise physical and chemical composition with a rapid development speed rate that allows different terrains to be simulated is required. However, existing lunar regolith simulants, designed for 20th-century exploration paradigms, are not sufficient to meet the requirements of modern space exploration. In order to prepare for the latest trends in space exploration, it is necessary to innovate the methodology for producing simulants. In this study, the basic framework for lunar regolith simulant development was established to realize this goal. The framework not only has a sample database and a database of potential simulation target compositions, but also has a built-in function to automatically calculate the optimal material mixing ratio through the particle swarm optimization algorithm to reproduce the target simulation, enabling fast and accurate simulant development. Using this framework, we anticipate a more agile response to the evolving needs toward simulants for space exploration.

An implementation of 2D/3D Complex Optical System and its Algorithm for High Speed, Precision Solder Paste Vision Inspection (솔더 페이스트의 고속, 고정밀 검사를 위한 이차원/삼차원 복합 광학계 및 알고리즘 구현)

  • 조상현;최흥문
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.41 no.3
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    • pp.139-146
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    • 2004
  • A 2D/3D complex optical system and its vision inspection algerian is proposed and implemented as a single probe system for high speed, precise vision inspection of the solder pastes. One pass un length labeling algorithm is proposed instead of the conventional two pass labeling algorithm for fast extraction of the 2D shape of the solder paste image from the recent line-scan camera as well as the conventional area-scan camera, and the optical probe path generation is also proposed for the efficient 2D/3D inspection. The Moire interferometry-based phase shift algerian and its optical system implementation is introduced, instead of the conventional laser slit-beam method, for the high precision 3D vision inspection. All of the time-critical algorithms are MMX SIMD parallel-coded for further speedup. The proposed system is implemented for simultaneous 2D/3D inspection of 10mm${\times}$10mm FOV with resolutions of 10 ${\mu}{\textrm}{m}$ for both x, y axis and 1 ${\mu}{\textrm}{m}$ for z axis. Experiments conducted on several nBs show that the 2D/3D inspection of an FOV, excluding an image capturing, results in high speed of about 0.011sec/0.01sec, respectively, after image capturing, with $\pm$1${\mu}{\textrm}{m}$ height accuracy.

Cache-Friendly Adaptive Video Streaming Framework Exploiting Regular Expression in Content Centric Networks (콘텐트 중심 네트워크에서 정규표현식을 활용한 캐시친화적인 적응형 스트리밍 프레임워크)

  • Son, Donghyun;Choi, Daejin;Choi, Nakjung;Song, Junghwan;Kwon, Ted Taekyoung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.9
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    • pp.1776-1785
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    • 2015
  • Content Centric Network (CCN) has been introduced as a new paradigm due to a shift of users's perspective of using Internet from host-centric to content-centric. On the other hand, a demand for video streaming has been increasing. Thus, Adaptive streaming has been introduced and researched for achieving higher user's satisfaction. If an architecture of Internet is replaced with CCN architecture, it is necessary to consider adaptive video streaming in CCN according to the demand of users. However, if the same rate decision algorithm used in Internet is deployed in CCN, there are a limitation of utilizing content store (CS) in CCN router and a problem of reflecting dynamic requirements. Therefore, this paper presents a framework adequate to CCN protocol and cache utilization, adapting content naming method of exploiting regular expression to the rate decision algorithm of the existing adaptive streaming. In addition, it also improves the quality of video streaming and verifies the performance through dynamic expression strategies and selection algorithm of the strategies.

A Versatile Reed-Solomon Decoder for Continuous Decoding of Variable Block-Length Codewords (가변 블록 길이 부호어의 연속 복호를 위한 가변형 Reed-Solomon 복호기)

  • 송문규;공민한
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.3
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    • pp.187-187
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    • 2004
  • In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

A Versatile Reed-Solomon Decoder for Continuous Decoding of Variable Block-Length Codewords (가변 블록 길이 부호어의 연속 복호를 위한 가변형 Reed-Solomon 복호기)

  • 송문규;공민한
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.3
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    • pp.29-38
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    • 2004
  • In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.