• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.49-51
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• 2008

본 논문은 중용량급 전원회로의 구성을 간략화 할 수 있는 절연형 AC-DC 컨버터의 구조와 그 제어 방법을 제안한다. 제안하는 회로의 구조는 병렬 전력 처리를 기반으로 한다. 병렬 모듈의 기능을 각각 AC 입력 전류의 위상을 제어하는 역률개선(PFC) 기능과, 콘덴서에 저장된 에너지를 이용하여 DC 전압을 생성하는 DC-DC 컨버터의 기능으로 분리한다. 병렬 모듈의 최종 출력단을 서로 직렬 연결하여, PFC 모듈이 생성한 전압과 DC-DC 컨버터 모듈이 생성한 전압을 서로 더해서 출력하는 구조이다. 이러한 구조를 통해서 기존의 병렬형 AC-DC 컨버터에 대비하여 반도체 소자의 내압을 감소시킬 수 있고, 최종 DC 전압의 동작응답특성 향상이 가능하다. 회로의 동작모드 분석이 실시되었고, 제어기 구현 방법이 제시되었다. 제안된 구조는 PDP 전원회로에의 응용을 위해서 400W(출력전압-200V, 출력전류-2A)급 실험용 회로를 구현하여 동작검증을 실시하였다.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.55 no.8
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• pp.329-333
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• 2006

We investigated the quench characteristics of a flux-lock type superconducting fault current limiter (SFCL) depending on the number of the serial connection between the superconducting elements at the subtractive polarity winding of a transformer. The flux-lock type SFCL consists of two coils. The primary coil is wound in parallel to the secondary coil through an iron core, and the secondary coil is connected to the superconducting elements in series. The operation of the flux-lock type SFCL can be divided into the subtractive and the additive polarity windings depending on the winding directions between the primary and secondary coils. In this paper, the analyses of voltage, current, and resistance of superconducting elements in serial connection were performed to increase the power capacity of flux-lock type SFCL. The power burden was reduced through the simultaneous quenching between the superconducting elements. This enabled the flux-lock type SFCL to be easy to increase the capacity of power system.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.9
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• pp.856-862
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• 2005

A flux-lock type SFCL consists of two coils, which are wound in parallel each other through an iron core, and a HTSC thin film connected in series with coil 2. If the current of the HTSC thin film exceeds its critical current by the fault accident, the resistance generated of the HTSC thin film, and thereby the fault current can be limited by the impedance of the flux-lock type SFCL. The amplitude of fault current can be set by the impedance of the flux-lock type SFCL. In this paper, we investigated the variance of the limiting current due to the ratio of inductances between coil 1 and coil 2 in the flux-lock type SFCL through the computer simulations and short circuit tests. In addition, both the simulation results and experimental ones were compared each other. From the comparison of both the results, the simulation results agreed well with the experimental ones.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.259-261
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• 2000

UPFC(Unified Power Flow Controller) consists of two voltage sourced converter(VSC)s inserted into AC system through series and parallel coupling transformer, where two VSCs are linked by capacitor at DC-side. Since VSC acts as an AC voltage source behind a reactance, where both magnitude and phase angle of the source are controllable, UPFC can be represented by the equation related to input-output relation of two VSCs. Voltage control of DC-link capacitor provides the path of real power flow between two VSCs. While UPFC is controlled for maintaining the given reference value in steady state, it should be controlled for damping power oscillation in dynamics. For such a control objective, the control strategy based on the energy function was proposed and has been shown to be effect and robust for damping power oscillation of power system. In this paper, UPFC model based on the VSC was analysed and applied to power-flow control and stability analysis. The control strategy based on the energy function is adopted for damping power oscillation of power system. The effectiveness of proposed control strategy was verified by simulation study

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.4
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• pp.363-369
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• 2005

we compared the operating characteristics between flux-lock type and resistive type superconducting fault current limiters(SFCLs). Flux-lock type SFCL consists of two coils, which are wound in parallel each other through an iron core, and a high-Tc superconducting(HTSC) element is connected with coil 2 in series. The the flux-lock type SFCL can be divided into the subtractive polarity winding and the additive polarity winding operations according to the winding directions between the coil 1 and coil 2. It was confirmed from experiments that flux-lock type SFCL could improve both the quench characteristics and the transport capacity compared to the resistive type SFCL, which means, the independent operation of HTSC element.

• Proceedings of the KSRS Conference
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• v.1
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• pp.220-223
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• 2006

The COMS(Communication, Ocean and Meteorological Satellite) EPS(Electrical Power Subsystem) is derived from an enhanced Eurostar 3000 EPS which is fully autonomous operation in normal conditions or in the event of a failure and provides a high level of reconfiguration capability and flexibility. This paper introduces the COMS EPS preliminary design result. The COMS EPS consists of a battery, a solar array wing, a PSR(Power Supply Regulator), a PRU(Pyrotechnic Unit), a SADM(Solar Array Drive Mechanism) and relay and fuse brackets. This can offer a bus power capability of 3 kW. The solar array is made of a deployable wing with two panels. One type of solar cells is selected as GaAs/Ge triple junction cells. Li-ion battery is base lined with ten series cell module of five cells in parallel. PSR associated with battery and solar array generates a power bus fully regulated 50 V. Power bus is centralised protection and distribution by relay and fuse brackets. PRU provides power for firing actuators devices. The solar array wing is routed by the SADM under control of the AOCS(Attitude Orbit Control Subsystem). The control and monitoring of the EPS especially of the battery, is performed by the PSR in combination with on-board software.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.4
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• pp.46-52
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• 2009

In this paper, a novel VCO (Voltage Controlled Oscillator) structure is proposed to achieve the characteristic of low phase noise and a wide frequency tuning range. The proposed scheme adopts an impedance transforming technique to change a series resonance into a parallel resonance for maximizing the susceptance slope parameter. The manufactured VCO shows a frequency tuning bandwidth of 600MHz from 10.1GHz to 10.7GHz with a tuning voltage varying from 0 to 9V, an excellent phase noise below -119dBc/Hz@1MHz offset. The harmonic suppression is measured above 28dB.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.3
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• pp.190-198
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• 2018

This paper proposes a nonisolated, bidirectional, soft-switching DC - DC converter with PWM plus phase shift (PPS) control. The proposed converter has an input-parallel/output-series configuration and can achieve the interleaving effect and high voltage gains, resulting in decreased voltage ratings in all related devices. The proposed converter can operate under zero-voltage switching (ZVS) conditions for all switches in continuous conduction mode. The power flow of the proposed converter can be controlled by changing the phase shift angle, and the duty is controlled to balance the voltage of four high voltage side capacitors. The PPS control device of the proposed converter is simple in structure and presents symmetrical switching patterns under a bidirectional power flow. The PPS control also ensures ZVS during charging and discharging at all loads and equalizes the voltage ratings of the output capacitors and switches. To verify the validity of the proposed converter, an experimental investigation of a 2 kW prototype is performed in both charging and discharging modes under different load conditions and a bidirectional power flow.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.99-106
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• 2004

In this Paper, the matched filter for searching initial synchronization in DSSS (direct sequence spread spectrum) receiver is studied. The matched filter with a single data flow path is described which can be presented by HDL (Hardware Description Language). In order to improve the processing time of operations for the filter, equations are arranged to represent two data flow paths and the associated hardware model is proposed. The model has an architecture based on parallelism and pipeline for fast processing, in which two data flow paths with a series of memory, multiplier and accumulator are placed in parallel. The performance of the model is analyzed and compared with the matched filter with a single data flow path.

• Proceedings of the KIEE Conference
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• summer
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• pp.518-520
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• 2004

In these days, there is a demand to develop fault current limiters(FCLs) to reduce excessive fault current and protect electrical equipments which are installed in the transmission and distribution power systems. We considered the resistive superconducting FCLs among the various kinds of FCLs. In this study, in order to develop the resistive superconducting FCL of 6.6kV 200A $3\phi$, we designed the new mask pattern for etching YBCO films by means of numerical analysis method, current limiting experiments and visualization of bubbles in films and investigated dielectric performance of the designed mask by using elecrtostatic numerical analysis method and breakdown experiments. We etched YBCO films by using the newly designed mask, connected the etched films in series and in parallel, and designed the 6.6kV resistive SFCL and then we observed the current limiting characteristics of the SFCL.