• Journal of Korean Society for Quality Management
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• v.17 no.2
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• pp.121-141
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• 1989

This paper is concerned with a development and evaluation of heuristics for the multi-stage sequence dependent flowshop sequencing. Eighteen heuristics, CAM1, CAM2, and etc., are proposed. The performance measure is a makespan which is to be minimized. The experiment for each algorithm is designed for a 4*3*3 factorial design with 360 observations. The experimental factors are PS(ratio of processing times to setup times), M(number of machines), N(number of jobs). The makespan of the proposed heuristics is compared with the optimal makespan obtained by the complete enumeration of schedules. This yardstick of comparison is called a relative error. The mean relative errors of the eighteen heuristics are from 2.048% to 8.717%. The computational results are analysed using SPSS. The experimental results show that the three factors are statistically significant at 5% level. The simulation for the large size problems is conducted to show having the similar computational results like the small size problems.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.35 no.1
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• pp.79-86
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• 2012

This study focuses on the problem of scheduling wafer lots of several recipe(operation condition) types in the photolithography workstation in a semiconductor wafer fabrication facility, and sequence-dependent recipe set up times may be required at the photolithography machines. In addition, a lot is able to be operated at a machine when the reticle(mask) corresponding to the recipe type is set up in the photolithography machine. We suggest various heuristic algorithms, in which developed recipe selection rules and lot selection rules are used to generate reasonable schedules to minimizing the total weighted flowtime. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the total weighted flowtime of the wafer lots with ready times.

• Journal of the Korean Operations Research and Management Science Society
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• v.13 no.1
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• pp.13-13
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• 1988

This paper considers the sequencing problem in mixed model assembly lines with hybrid workstation types and sequence-dependent setup times. Computation time is often a critical factor in choosing a method of determining the sequence. We develop a mathematical formulation of the problem to minimize the overall length of a line, and present a tabu search technique which can provide a near optimal solution in real time. The proposed technique is compared with a genetic algorithm and a branch-and-bound method. Experimental results are reported to demonstrate the efficiency of the technique.

• IE interfaces
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• v.15 no.4
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• pp.338-348
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• 2002

In this paper, we present a restricted tabu search(RTS) algorithm that schedules jobs on identical parallel machines in order to minimize the maximum lateness of jobs. Jobs have release times and due dates. Also, sequence-dependent setup times exist between jobs. The RTS algorithm consists of two main parts. The first part is the MATCS(Modified Apparent Tardiness Cost with Setups) rule that provides an efficient initial schedule for the RTS. The second part is a search heuristic that employs a restricted neighborhood generation scheme with the elimination of non-efficient job moves in finding the best neighborhood schedule. The search heuristic reduces the tabu search effort greatly while obtaining the final schedules of good quality. The experimental results show that the proposed algorithm gives better solutions quickly than the existing heuristic algorithms such as the RHP(Rolling Horizon Procedure) heuristic, the basic tabu search, and simulated annealing.

• Journal of Korean Institute of Industrial Engineers
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• v.33 no.3
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• pp.329-338
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• 2007

This paper presents a dispatching algorithm for nonidentical parallel machines problem considering rework, sequence dependent setup times and release times. For each pair of a machine and a job type, rework probability of each job on a machine can be known through historical data acquisition. The heuristic scheduling scheme named by EDDR (Earliest Due Date with Rework probability) algorithm is proposed in this paper making use of the rework probability. The proposed dispatching algorithm is measured by two objective function value: 1) total tardiness and 2) the number of reworked jobs, respectively. The extensive computational results show that the proposed algorithm gives very efficient schedules superior to the existing dispatching algorithms.

• Journal of Korean Society for Quality Management
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• v.47 no.4
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• pp.823-835
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• 2019

Purpose: This study deals with a production planning and scheduling problem to minimize the total weighted tardiness on hybrid flow shop with sets of non-identical parallel machines on stages, where parallel machines in the set are dedicated to perform specific subsets of jobs and sequence-dependent setup times are also considered. Methods: A two-stage approach, that applies MILP model in the 1st stage and dispatching rules in the 2nd stage, is proposed in this paper. The MILP model is used to assign jobs to a specific machine in order to equalize the workload of the machines at each stage, while new dispatching rules are proposed and applied to sequence jobs in the queue at each stage. Results: The proposed two-stage approach was implemented by using a commercial MILP solver and a commercial simulation software and a case study was developed based on the spark plug manufacturing process, which is an automotive component, and verified using the company's actual production history. The computational experiment shows that it can reduce the tardiness when used in conjunction with the dispatching rule. Conclusion: This proposed two-stage approach can be used for HFS systems with dedicated machines, which can be evaluated in terms of tardiness and makespan. The method is expected to be used for the aggregated production planning or shop floor-level production scheduling.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.38 no.4
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.