• 한국정밀공학회지
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• 제17권4호
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• pp.106-113
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• 2000

One of the recent changes in machining technology is rapid application of micro- and high precision grinding processes. A fine groove generation is necessary for the fabrication of optics, electronics and semiconductor parts. Slot grinding is very efficient for the generation of micro ordered groove with hard and brittle materials. In the process of slot grinding, chipping at the sharp edges and microcracks of the ground grooves are inevitable defects. Chipping should be reduced for the improvement of surface integrity. Mechanical contact with diamond grits causes microcracks at the grooves. This damage resides subsurface, and can be the cause of failure of the punch die. This paper deals with chipping generation at the sharp edges, surface integrity of side groove and fracture strength is related to the microcracks in the slot grinding.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 디스플레이 광소자분야
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• pp.203-205
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• 2003

레이저 다이오드를 p-side-down 방식으로 본딩하기 위하여 AuSn 솔더합금을 증착한 후 온도와 압력, 시간을 변화시켜 본딩상태를 조사하였다. CuW위에 adhsion layer와 확산방지층을 각각 $500{\AA}$과 $2000{\AA}$을 증착하였으며 솔더층으로 AuSn을 $2.6{\mu}m$ 증착 하였다. 열처리는 질소 분위기에서 행하였으며, 표면의 거칠기는 AFM으로 측정하였다.

• Design & Manufacturing
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• 제12권1호
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• pp.47-51
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• 2018

As the IT industry rapidly progresses, the functions of electronic devices and display devices are integrated with high density, and the model is changed in a short period of time. To implement the integration technology, a uniform micro-pattern implementation technique to drive and control the product is required. The most important technology for the micro pattern generation is the exposure processing technology. Failure to implement the basic pattern in this process cannot satisfy the demands in the manufacturing field. In addition, the conventional exposure method of the mask method cannot cope with the small-scale production of various types of products, and it is not possible to implement a micro-pattern, so an alternative technology must be secured. In this study, the technology to implement the required micro-pattern in semiconductor processing is presented through the photolithography process and plasma etching.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.31-34
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• 2002

For the mold die sticking mechanism, the major explanation is that the silica as a filler in EMC (epoxy molding compound) wears die surface to be roughened, which results in increase of adhesion strength. As the sticking behavior, however, showed strong dependency on the EMC models based on the experimental results from different semiconductor manufacturers, chemisorption or acid-base interaction is apt to be also functioning as major mechanisms. In this investigation, the plasma source ion implantation (PSII) using $O_2, N_2$, and $CF_4$ modifies sample surface to form a new dense layer and improve surface hardness, and change metal surface condition from hydrophilic to hydrophobic or vice versa. Through surface energy quantification by measuring contact angle and surface ion coupling state analysis by Auger, major governing mechanism for sticking issue was figured out to be a complex of mechanical and chemical factors.

• 반도체디스플레이기술학회지
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• 제5권1호
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• pp.5-11
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• 2006

One of the most important is to insure that a new circuit design is qualified far release before it is scheduled for manufacturing, test, assembly and delivery. Due to various causes, there happens to be a low yield in the wafer process. Wafer test is a critical process in analyzing the chip characteristics in the EDS(electric die sorting) using analytic tools -wafer map, wafer summary and datalog. In this paper, we propose new analytic map algorithms for DDI chip test data. Using the proposed analytic map algorithms, we expect to improve the yield, quality and analysis time.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• 한국산학기술학회논문지
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• 제21권12호
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• pp.261-267
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• 2020

휴대용기기에 대한 경박단소 및 빠른 속도에 대한 요구는 반도체 패키징 기술에도 변화를 가져왔다. 이에 대한 대응의 하나로 stacked chip scale package(SCSP)가 업계에서 사용되고 있다. SCSP를 구현하기 위한 핵심소재 중의 하나가 die attach film(DAF)이다. 특히, 다이와 기판을 접착하거나 다이와 다이를 접착하는 경우, DAF의 접착필름은 기판의 단차나 본딩 와이어 사이를 기공의 발생 없이 채우기 위해 우수한 고온 유동성이 요구된다. 그러나 이 경우 경화 크랙의 발생을 최소화하기 위해 2단계 경화가 종종 요구되나, 공정시간 단축을 위해서는 1단계 경화가 바람직하다. 본 연구에서는 DAF 접착필름의 조성물을 경화 성분(에폭시 수지), 유연 성분(고무성분), 딱딱한 성분(페녹시수지, 실리카), 3개 군으로 분류하고, 조성물의 변화에 따른 1단계 경화시 경화 크랙, 고온 유동성, die attach (DA) 기공발생에 대한 영향을 혼합물 실험 설계법를 통해 살펴보았다. 경화 크랙은 딱딱한 성분 함량에 가장 크게 영향을 받았으며, 함량이 증가할수록 경화 크랙이 감소하였다. DA 기공의 발생은 딱딱한 성분의 함량이 감소할수록 감소하였으며, 특히, 딱딱한 성분의 함량이 적은 경우는 경화 성분의 함량이 감소할수록, 기공의 발생이 억제되었다. 고온 유동성은 100℃ 저장탄성 계수와 120℃에서의 블리드 아웃(BL-120)으로 평가되었다. 100℃의 고온 저장탄성률은 딱딱한 성분의 감소가 중요하였고, 유동성 지표인 BL-120의 경우는 경화 성분의 함량의 증가와 딱딱한 성분의 감소가 동시에 중요하였다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1995년도 추계 학술발표 강연 및 논문개요집
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• pp.3-3
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• 1995

Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 추계학술대회 논문집
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• pp.233-234
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• 2006

• 한국시뮬레이션학회논문지
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• 제12권3호
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• pp.13-20
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• 2003

Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer