• Proceedings of the Korean Society of Precision Engineering Conference
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• 1994.10a
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• pp.670-675
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• 1994

Yhis paper describes a fault diagnosis simulation of the Real-Time Multiple Fault Dignosis System (RTMFDS) for forcasting faults in a system and deciding current machine state from signal information. Comparing with other diagnosis system for single fault,the system developed deals with multiple fault diagnosis,comprising two main parts. One is a remotesignal generating and transimission terminal and the other is a host system for fault diagnosis. Signal generator generate the random fault signal and the image information, and send this information to host. Host consists of various modules and agents such as Signal Processing Module(SPM) for sinal preprocessing, Performence Monotoring Module(PMM) for subsystem performance monitoring, Trigger Module(TM) for multi-triggering subsystem fault diagnosis, Subsystem Fault Diagnosis Agent(SFDA) for receiving trigger signal, formulating subsystem fault D\ulcornerB and initiating diagnosis, Fault Diagnosis Module(FDM) for simulating component fault with Hierarchical Artificial Neural Network (HANN), numerical models and Hofield network,Result Agent(RA) for receiving simulation result and sending to Treatment solver and Graphic Agent(GA). Each agent represents a separate process in UNIX operating system, information exchange and cooperation between agents was doen by IPC(Inter Process Communication : message queue, semaphore, signal, pipe). Numerical models are used to deseribe structure, function and behavior of total system, subsystems and their components. Hierarchical data structure for diagnosing the fault system is implemented by HANN. Signal generation and transmittion was performed on PC. As a host, SUN workstation with X-Windows(Motif)is used for graphic representation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.9
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• pp.113-119
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• 2005

The methods that are used for receiving data from attached devices under real-time preemptive multi-task operating system (OS) by general processors can be categorized as polling and interrupt driven. The technical approach to these methods may be different due to the application specific scheduling policy of the OS and the programming architecture of the flight software. It is one of the most important requirements on the development of the flight software to process the data received from satellite subsystems or components with the exact timeliness and accuracy. This paper presents the analysis of the I/O method of device related scheduling mechanism and the reliable data I/O methods between processor and devices.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.371-374
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• 2004

Induction motors are a critical component of many industrial processes and are frequently integrated in commercially available equipment. Safety, reliability, efficiency, and performance are some of the major concerns of induction motor applications. Preventive maintenance of induction motors has been a topic great interest to industry because of their wide range application of industry. Since the use of mechanical sensors, such as vibration probes, strain gauges, and accelerometers is often impractical, the motor current signature analysis (MACA) techniques have gained murk popularity as diagnostic tool. Fault tolerant control (FTC) strives to make the system stable and retain acceptable performance under the system faults. All present FTC method can be classified into two groups. The first group is based on fault detection and diagnostics (FDD). The second group is independent of FDD and includes methods such as integrity control, reliable stabilization and simultaneous stabilization. This paper presents the fundamental FDD-based FTC methods, which are capable of on-line detection and diagnose of the induction motors. Therefore, our group has developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. This paper presents its architecture. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module is checking stator current, voltage, temperatures, vibration and speed of the motor. The DSPs share information from each sensor or DSP through DPRAM with hardware implemented semaphore. And it communicates the motor status through field bus (CAN, RS485). From the designed system, we get primitive sensors data for the case of normal condition and two abnormal conditions of 3 phase induction motor control system is implemented. This paper is the first step to drive multi-motors with serial communication which can satisfy the real time operation using CAN protocol.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.4
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• pp.291-303
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• 2009

Round robin based proportional share scheduling(RRPS) defines weight which determines share for each task and allocates CPU resource to each task in proportional to its respective weight. RRPS uses fairness as the measure of performance and aims at high fairness of scheduling. However, researches for scheduling fairness problem due to synchronization among tasks have been rarely investigated. In this paper, we discuss that scheduling delay due to synchronization may result high unfairness in RRPS. We explain such a situation as weight inversion. We then propose weight inheritance protocol(WIP), a synchronization mechanism, that prevents weight inversion. We also show that WIP can reduce unfairness using fairness analysis and simulation.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.3
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• pp.193-197
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• 2009

In this paper, we study on design of vehicle control system which is based on ${\mu}C/OS-II$, We component a electric motor drive system for simulator because the most of vehicle part use electric motor for actuator. We use the XC2287 microcontroller which is often used vehicle body controller because XC2287 guarantee high confidence and durability in vehicle industry. The electric motor control system derive PWM from general I/O port in XC2287 microcontroller. The signal is supplied at electric motor after amplifying that using driver circuit. The user control duty of PWM signal through controlling potentiometer which is connected to XC2287. through that, the user control speed of electric motor. we synchronize both input process via controlling potentiometer and PWM output process using semaphore. we verify porting of ${\mu}C/OS-II$ via experimentation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.5
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• pp.385-393
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• 2021

This study proposes a multi-core-based controller design for an ESC(Electronic Stability Control) system in an automotive multi-core processor. Considering the architectures of an automotive multi-core processor and an ESC system, the overall execution time has been optimized for multi-core platforms. The function module assignment, synchronization between cores, and memory assignment for core-dependent variables in automotive multi-core systems are evaluated. The ESC controller comprising five function modules is used herein. Based on the proposed design, the single-core controller is extended to multi-core controllers. Using multi-core optimization methods, such as function module assignment, semaphore, interrupt awakening, and variable assignment over cores, the ESC system is redesigned to a multi-core controller. Experimental results reveal that the execution time for the multi-core processor is reduced by 59.7% compared with that for the single-core processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.646-680
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• 2000

In this paper, we discuss the design and implementation of a concurrency control manager for a main memory DBMS(MMDBMS). Since an MMDBMS, unlike a disk-based DBMS, performs all of data update or retrieval operations by accessing main memory only, the portion of the cost for concurrency control in the total cost for a data update or retrieval is fairly high. Thus, the development of an efficient concurrency control manager highly accelerates the performance of the entire system. Our concurrency control manager employs the 2-phase locking protocol, and has the following characteristics. First, it adapts the partition, an allocation unit of main memory, as a locking granule, and thus, effectively adjusts the trade-off between the system concurrency and locking cost through the analysis of applications. Second, it enjoys low locking costs by maintaining the lock information directly in the partition itself. Third, it provides the latch as a mechanism for physical consistency of system data. Our latch supports both of the shared and exclusive modes, and maximizes the CPU utilization by combining the Bakery algorithm and Unix semaphore facility. Fourth, for solving the deadlock problem, it periodically examines whether a system is in a deadlock state using lock waiting information. In addition, we discuss various issues arising in development such as mutual exclusion of a transaction table, mutual exclusion of indexes and system catalogs, and realtime application supports.