• Title/Summary/Keyword: Science & Engineering

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Flexible, Transparent Thin-Film Transistors Fabricated by Ink-Jet Printing with Carbon Nanotube-Based Conducting Ink

  • Lee, Yeon-Ju;Lee, Woo-Suk;Jeong, Soo-Kyeong;Choi, Seok-Ju;Kim, Hye-Min;Chun, Jin-Young;Kim, Sung-Ho;Geckeler, Kurt E.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.920-922
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    • 2009

  • Flexible, transparent thin-film transistor with active layers composed of carbon nanotube-based conducting ink were fabricated on a plastic substrate by ink-jet printing. The properties of the formulated conducting ink containing carbon nanotubes, a conducting polymer, and additives were characterized and optimized. The conducting ink was applied to flexible thin-film transistors using ink-jet printing.

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A Review of Structural Testing Methods for ASIC based AI Accelerators

  • Umair, Saeed;Irfan Ali, Tunio;Majid, Hussain;Fayaz Ahmed, Memon;Ayaz Ahmed, Hoshu;Ghulam, Hussain
    • International Journal of Computer Science & Network Security
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    • v.23 no.1
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    • pp.103-111
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    • 2023

  • Implementing conventional DFT solution for arrays of DNN accelerators having large number of processing elements (PEs), without considering architectural characteristics of PEs may incur overwhelming test overheads. Recent DFT based techniques have utilized the homogeneity and dataflow of arrays at PE-level and Core-level for obtaining reduction in; test pattern volume, test time, test power and ATPG runtime. This paper reviews these contemporary test solutions for ASIC based DNN accelerators. Mainly, the proposed test architectures, pattern application method with their objectives are reviewed. It is observed that exploitation of architectural characteristic such as homogeneity and dataflow of PEs/ arrays results in reduced test overheads.

  • https://doi.org/10.22937/IJCSNS.2023.23.1.14 인용 PDF